| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveInterval.cpp | 1148 OS << " updater with gap = " << (ReadI - WriteI) in print()
1151 for (const auto &S : make_range(LR->begin(), WriteI)) in print()
1195 WriteI = ReadI = LR->begin(); in add()
1205 if (ReadI != WriteI) in add()
1208 if (ReadI == WriteI) in add()
1209 ReadI = WriteI = LR->find(Seg.start); in add()
1212 *WriteI++ = *ReadI++; in add()
1242 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
1243 WriteI[-1].end = std::max(WriteI[-1].end, Seg.end); in add()
1248 if (WriteI != ReadI) { in add()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX.td | 51 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
201 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
205 def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
209 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
225 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
229 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
235 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
264 def : InstRW<[WriteI], (instrs COPY)>;
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| D | AArch64SchedA53.td | 59 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
157 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
161 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
165 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
181 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
185 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
191 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
202 def : InstRW<[WriteI], (instrs COPY)>;
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| D | AArch64SchedThunderX2T99.td | 416 def : WriteRes<WriteI, [THX2T99I012]> {
422 def : InstRW<[WriteI],
435 def : InstRW<[WriteI], (instrs COPY)>;
582 // NOTE: Handled by WriteI.
599 // NOTE: Handled by WriteLD, WriteI.
720 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>;
721 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>;
722 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>;
723 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>;
724 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>;
[all …]
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| D | AArch64SchedKryo.td | 65 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
129 def : InstRW<[WriteI], (instrs COPY)>;
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| D | AArch64SchedA57.td | 73 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
129 def : InstRW<[WriteI], (instrs COPY)>;
144 SchedVar<NoSchedPred, [WriteI]>]>;
582 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
588 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
595 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
601 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
611 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
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| D | AArch64Schedule.td | 24 def WriteI : SchedWrite; // ALU
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| D | AArch64SchedFalkor.td | 70 def : WriteRes<WriteI, []> { let Unsupported = 1; }
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| D | AArch64SchedCyclone.td | 126 SchedVar<NoSchedPred, [WriteI]>]>;
150 def : WriteRes<WriteI, [CyUnitI]>;
292 def : InstRW<[WriteI], (instrs ISB)>;
359 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
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| D | AArch64InstrFormats.td | 1749 Sched<[WriteI, ReadI]> {
1784 Sched<[WriteI, ReadI]> {
1809 Sched<[WriteI, ReadI, ReadI]> {
1824 Sched<[WriteI, ReadI, ReadI]> {
1852 Sched<[WriteI, ReadI, ReadI]> {
2079 Sched<[WriteI]> {
2143 Sched<[WriteI, ReadI]> {
2174 Sched<[WriteI, ReadI]> {
2200 Sched<[WriteI, ReadI, ReadI]>;
2616 Sched<[WriteI, ReadI]> {
[all …]
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| D | AArch64SchedExynosM3.td | 196 def : SchedAlias<WriteI, M3WriteA1>;
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| D | AArch64SchedExynosM5.td | 542 def : SchedAlias<WriteI, M5WriteA1W>;
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| D | AArch64SchedExynosM4.td | 509 def : SchedAlias<WriteI, M4WriteA1>;
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| D | AArch64InstrInfo.td | 1940 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSubtargetInfo.inc | 1509 { 1, 1028}, // #2 WriteI
1534 { 1, 1028}, // #27 WriteI
1536 { 1, 1028}, // #29 WriteI
1646 { 5, 1028}, // #139 WriteI
1655 { 3, 1028}, // #148 WriteI
1667 { 3, 1028}, // #160 WriteI
1669 { 3, 1028}, // #162 WriteI
1797 { 1, 1028}, // #290 WriteI
1799 { 1, 1028}, // #292 WriteI
1814 { 1, 1028}, // #307 WriteI
[all …]
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| D | AArch64GenInstrInfo.inc | 5423 WriteI = 7,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | LiveInterval.h | 930 LiveRange::iterator WriteI; variable
|