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Searched refs:WriteMask (Results 1 – 25 of 75) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/i915/
Di915_fpc_optimize.c230 o->WriteMask = i->WriteMask; in copy_dst_reg()
456 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_X) in i915_fpc_optimize_mov_after_mov()
458 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Y) in i915_fpc_optimize_mov_after_mov()
460 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_Z) in i915_fpc_optimize_mov_after_mov()
462 if (dst_reg2->Register.WriteMask & TGSI_WRITEMASK_W) in i915_fpc_optimize_mov_after_mov()
465 dst_reg2->Register.WriteMask |= dst_reg1->Register.WriteMask; in i915_fpc_optimize_mov_after_mov()
502 current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
504 current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
506 next->FullInstruction.Dst[0].Register.WriteMask)) { in i915_fpc_optimize_mov_after_alu()
512 next->FullInstruction.Dst[0].Register.WriteMask, in i915_fpc_optimize_mov_after_alu()
[all …]
/third_party/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_pair_translate.c92 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; in classify_instruction()
93 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; in classify_instruction()
277 inst->DstReg.WriteMask); in set_pair_instruction()
288 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
295 inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
297 GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
305 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
309 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3); in set_pair_instruction()
310 if (pair->Alpha.WriteMask) { in set_pair_instruction()
Dradeon_program_tex.c92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in projective_divide()
172 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in radeonTransformTEX()
182 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
193 inst_mul->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
209 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
310 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
332 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
341 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
352 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
367 inst_add->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
[all …]
Dradeon_dataflow_deadcode.c41 unsigned char WriteMask:4; member
154 usedmask = *pused & inst->U.I.DstReg.WriteMask; in update_instruction()
159 insts->WriteMask |= usedmask; in update_instruction()
221 mark_used(&s, RC_FILE_OUTPUT, inst->U.I.DstReg.Index, inst->U.I.DstReg.WriteMask); in rc_dataflow_deadcode()
246 unsigned int writemask = ptr->U.I.DstReg.WriteMask; in rc_dataflow_deadcode()
316 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask; in rc_dataflow_deadcode()
317 if (s.Instructions[ip].WriteMask) in rc_dataflow_deadcode()
333 usemask = s.Instructions[ip].WriteMask; in rc_dataflow_deadcode()
Dradeon_variable.c62 if (var_ptr->Dst.WriteMask == RC_MASK_W) { in rc_variable_change_dst()
138 unsigned int mask = var->Readers[i].WriteMask; in rc_variable_compute_live_intervals()
267 new->Dst.WriteMask = DstWriteMask; in rc_variable()
314 if (sub_inst->WriteMask) { in get_variable_pair_helper()
316 writemask = sub_inst->WriteMask; in get_variable_pair_helper()
408 inst->U.I.DstReg.WriteMask, &reader_data); in rc_get_variables()
456 writemask |= var->Dst.WriteMask; in rc_variable_writemask_sum()
587 var->Inst->IP, var->Dst.Index, var->Dst.WriteMask); in rc_variable_print()
Dr3xx_fragprog.c52 if (inst->DstReg.WriteMask & RC_MASK_Z) { in rc_rewrite_depth_out()
53 inst->DstReg.WriteMask = RC_MASK_W; in rc_rewrite_depth_out()
55 inst->DstReg.WriteMask = 0; in rc_rewrite_depth_out()
Dradeon_optimize.c459 reader_data->Writer->U.I.DstReg.WriteMask, in presub_scan_read()
588 unsigned dstmask = inst_add->U.I.DstReg.WriteMask; in peephole_add_presub_add()
661 if (!(inst_add->U.I.DstReg.WriteMask & (1 << i))) in peephole_add_presub_inv()
670 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv()
671 inst_add->U.I.DstReg.WriteMask in peephole_add_presub_inv()
701 d->Writer->File, d->Writer->Index, d->Writer->WriteMask)) { in omod_filter_reader_cb()
716 (mask & d->Writer->WriteMask)) { in omod_filter_writer_cb()
846 if (util_bitcount(writemask_sum) < util_bitcount(inst_mul->U.I.DstReg.WriteMask)) in peephole_mul_omod()
854 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
907 unsigned int orig_dst_wmask = inst->U.I.DstReg.WriteMask; in merge_movs()
[all …]
Dradeon_dataflow.c261 if (opcode->HasDstReg && inst->DstReg.WriteMask) in writes_normal()
262 cb(userdata, fullinst, inst->DstReg.File, inst->DstReg.Index, inst->DstReg.WriteMask); in writes_normal()
272 if (inst->RGB.WriteMask) in writes_pair()
273 cb(userdata, fullinst, RC_FILE_TEMPORARY, inst->RGB.DestIndex, inst->RGB.WriteMask); in writes_pair()
275 if (inst->Alpha.WriteMask) in writes_pair()
394 if (inst->RGB.WriteMask) { in remap_pair_instruction()
403 if (inst->Alpha.WriteMask) { in remap_pair_instruction()
486 new->WriteMask = mask; in add_reader()
898 if (sub_writer->WriteMask) { in rc_get_readers_sub()
900 sub_writer->DestIndex, sub_writer->WriteMask); in rc_get_readers_sub()
Dradeon_program_print.c164 if (dst.WriteMask != RC_MASK_XYZW) { in rc_print_dst_register()
166 rc_print_mask(f, dst.WriteMask); in rc_print_dst_register()
389 if (inst->RGB.WriteMask) in rc_print_pair_instruction()
391 (inst->RGB.WriteMask & 1) ? "x" : "", in rc_print_pair_instruction()
392 (inst->RGB.WriteMask & 2) ? "y" : "", in rc_print_pair_instruction()
393 (inst->RGB.WriteMask & 4) ? "z" : ""); in rc_print_pair_instruction()
428 if (inst->Alpha.WriteMask) in rc_print_pair_instruction()
Dradeon_program_alu.c105 dst.WriteMask = mask; in dstregtmpmask()
227 return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask); in try_to_reuse_dst()
334 if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) { in transform_LIT()
343 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in transform_LIT()
409 tempdst.WriteMask = RC_MASK_W; in transform_POW()
431 unsigned int mask = inst->U.I.DstReg.WriteMask; in transform_ROUND()
557 dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask), in transform_SSG()
684 dst.WriteMask = RC_MASK_XYZW; in transform_r300_vertex_fix_LIT()
712 dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask), in transform_r300_vertex_SEQ()
739 dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask), in transform_r300_vertex_SNE()
[all …]
Dradeon_emulate_branches.c78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; in handle_if()
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW; in inject_cmp()
298 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in fix_output_writes()
Dr3xx_vertprog.c197 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector1()
214 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector2()
231 t_dst_mask(vpi->DstReg.WriteMask), in ei_math1()
249 t_dst_mask(vpi->DstReg.WriteMask), in ei_lit()
317 t_dst_mask(vpi->DstReg.WriteMask), in ei_mad()
325 t_dst_mask(vpi->DstReg.WriteMask), in ei_mad()
359 t_dst_mask(vpi->DstReg.WriteMask), in ei_pow()
795 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in rc_vs_add_artificial_outputs()
827 add->U.I.DstReg.WriteMask = RC_MASK_X; in transform_negative_addressing()
Dradeon_compiler_util.c203 sub->WriteMask = rewrite_writemask(sub->WriteMask, conversion_swizzle); in rc_pair_rewrite_writemask()
235 sub->DstReg.WriteMask = in rc_normal_rewrite_writemask()
236 rewrite_writemask(sub->DstReg.WriteMask, conversion_swizzle); in rc_normal_rewrite_writemask()
Dradeon_pair_schedule.c654 rgb->Alpha.WriteMask = alpha->Alpha.WriteMask; in destructive_merge_instructions()
715 if (emitted->Prev->U.P.RGB.WriteMask) in presub_nop()
719 if (emitted->Prev->U.P.Alpha.WriteMask) in presub_nop()
881 unsigned int old_mask = pair_inst->RGB.WriteMask; in convert_rgb_to_alpha()
891 if (!pair_inst->RGB.WriteMask) in convert_rgb_to_alpha()
940 pair_inst->Alpha.WriteMask = RC_MASK_W; in convert_rgb_to_alpha()
960 pair_inst->RGB.WriteMask = 0; in convert_rgb_to_alpha()
/third_party/mesa3d/src/gallium/drivers/r300/compiler/tests/
Drc_test_helpers.c252 struct match_info WriteMask; member
285 tokens.WriteMask.String = dst_str + matches[3].rm_so; in init_rc_normal_dst()
286 tokens.WriteMask.Length = match_length(matches, 3); in init_rc_normal_dst()
311 if (tokens.WriteMask.Length == 0) { in init_rc_normal_dst()
312 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in init_rc_normal_dst()
314 inst->U.I.DstReg.WriteMask = 0; in init_rc_normal_dst()
316 if (tokens.WriteMask.String[0] != '.') { in init_rc_normal_dst()
320 for (i = 1; i < tokens.WriteMask.Length; i++) { in init_rc_normal_dst()
321 switch(tokens.WriteMask.String[i]) { in init_rc_normal_dst()
323 inst->U.I.DstReg.WriteMask |= RC_MASK_X; in init_rc_normal_dst()
[all …]
/third_party/mesa3d/src/mesa/main/
Dstencil.h76 ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[face]); in _mesa_stencil_is_two_sided()
83 (ctx->Stencil.WriteMask[0] != 0 || in _mesa_stencil_is_write_enabled()
85 ctx->Stencil.WriteMask[ctx->Stencil._BackFace] != 0)); in _mesa_stencil_is_write_enabled()
Dstencil.c267 if (ctx->Stencil.WriteMask[face] == mask) in _mesa_StencilMask()
271 ctx->Stencil.WriteMask[face] = mask; in _mesa_StencilMask()
275 if (ctx->Stencil.WriteMask[0] == mask && in _mesa_StencilMask()
276 ctx->Stencil.WriteMask[1] == mask) in _mesa_StencilMask()
280 ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask; in _mesa_StencilMask()
527 ctx->Stencil.WriteMask[0] = mask; in stencil_mask_separate()
531 ctx->Stencil.WriteMask[1] = mask; in stencil_mask_separate()
604 ctx->Stencil.WriteMask[0] = 0xFF; in _mesa_init_stencil()
605 ctx->Stencil.WriteMask[1] = 0xFF; in _mesa_init_stencil()
606 ctx->Stencil.WriteMask[2] = 0xFF; in _mesa_init_stencil()
/third_party/mesa3d/src/mesa/program/
Dprogramopt.c92 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); in insert_mvp_dp4_code()
163 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
175 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
190 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
321 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
342 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
356 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
369 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
381 inst->DstReg.WriteMask = WRITEMASK_XYZ; in _mesa_append_fog_code()
396 inst->DstReg.WriteMask = WRITEMASK_W; in _mesa_append_fog_code()
/third_party/skia/src/gpu/
DGrUserStencilSettings.h119 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask> struct Init {};
129 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask>
130 constexpr static Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask> StaticInit() { in StaticInit()
131 return Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>(); in StaticInit()
150 GrUserStencilOp PassOp, GrUserStencilOp FailOp, uint16_t WriteMask,
153 const Init<Ref, Test, TestMask, PassOp, FailOp, WriteMask>&) in GrUserStencilSettings()
157 Attrs::EffectiveWriteMask(WriteMask)}
161 Attrs::EffectiveWriteMask(WriteMask)} {
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_lowering.c72 dst->Register.WriteMask &= wrmask; in reg_dst()
73 assert(dst->Register.WriteMask); in reg_dst()
216 if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) { in transform_dst()
228 if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) { in transform_dst()
239 if (dst->Register.WriteMask & TGSI_WRITEMASK_W) { in transform_dst()
250 if (dst->Register.WriteMask & TGSI_WRITEMASK_X) { in transform_dst()
288 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_lrp()
336 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_frc()
382 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_pow()
441 if (dst->Register.WriteMask & TGSI_WRITEMASK_YZ) { in transform_lit()
[all …]
Dtgsi_transform.h253 reg->Register.WriteMask = writemask; in tgsi_transform_dst_reg()
305 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op1_inst()
332 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op2_inst()
362 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op3_inst()
390 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op1_swz_inst()
435 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op2_swz_inst()
489 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op3_swz_inst()
Dtgsi_exec.c2134 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_tex()
2178 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) { in exec_lodq()
2181 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) { in exec_lodq()
2193 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_lodq()
2204 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) { in exec_lodq()
2207 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) { in exec_lodq()
2314 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txd()
2391 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txf()
2399 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txf()
2430 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txq()
[all …]
Dtgsi_ureg.h80 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */ member
509 dst.WriteMask == 0; in ureg_dst_is_empty()
917 reg.WriteMask &= writemask; in ureg_writemask()
1021 dst.WriteMask = TGSI_WRITEMASK_XYZW; in ureg_dst_array_register()
1053 dst.WriteMask = TGSI_WRITEMASK_XYZW; in ureg_dst()
1145 dst.WriteMask = 0; in ureg_dst_undef()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c3120 unsigned write_mask = dst->Register.WriteMask; in r600_store_tcs_output()
4479 cf.comp_mask = inst->Dst[0].Register.WriteMask; in tgsi_dst()
4527 unsigned write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_64_params()
4622 write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_64_params()
4654 unsigned write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_64()
4690 if (inst->Dst[0].Register.WriteMask & (1 << i)) in tgsi_op3_64()
4711 unsigned write_mask = inst->Dst[0].Register.WriteMask; in tgsi_op2_s()
4800 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); in tgsi_ineg()
4804 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) in tgsi_ineg()
4831 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); in tgsi_dneg()
[all …]
/third_party/mesa3d/src/mesa/state_tracker/
Dst_atom_depth.c107 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff; in st_update_depth_stencil_alpha()
118 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff; in st_update_depth_stencil_alpha()

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