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Searched refs:XMM0 (Results 1 – 24 of 24) sorted by relevance

/third_party/mesa3d/src/mesa/x86/
Dcommon_x86_asm.S167 XORPS ( XMM0, XMM0 )
196 XORPS ( XMM0, XMM0 )
205 DIVPS ( XMM0, XMM1 )
Dassyntax.h224 #define XMM0 %xmm0 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
233 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
237 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
265 // case they use XMM0, otherwise it is the same as the common X86 calling
268 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
275 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
279 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
280 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
293 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
[all …]
DX86CallingConv.cpp80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
DX86CallLowering.cpp165 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2, in assignArg()
DX86RegisterInfo.cpp600 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
DREADME-SSE.txt807 This would be better kept in the SSE unit by treating XMM0 as a 4xfloat and
DX86RegisterInfo.td212 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
DX86InstrSSE.td6331 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6340 (VT (OpNode XMM0, VR128:$src2, VR128:$src1)))]>,
6348 (OpNode XMM0, (mem_frag addr:$src2), VR128:$src1))]>,
6377 def : Pat<(v4i32 (X86Blendv (v4i32 XMM0), (v4i32 VR128:$src1),
6380 def : Pat<(v2i64 (X86Blendv (v2i64 XMM0), (v2i64 VR128:$src1),
6502 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
6520 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
6624 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
6635 (memop addr:$src2), XMM0)),
6666 let Uses=[XMM0] in
DX86FastISel.cpp3125 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerArguments()
3462 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerCall()
DX86InstrCompiler.td477 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
497 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
DX86ISelLowering.cpp2727 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
3336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in get64BitArgumentXMMs()
4008 case X86::XMM0: ShadowReg = X86::RCX; break; in LowerCall()
4066 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in LowerCall()
47007 return std::make_pair(X86::XMM0, &X86::VR128RegClass); in getRegForInlineAsmConstraint()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86Operand.h321 return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem64_RC128()
324 return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem128_RC128()
330 return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15); in isMem256_RC128()
337 return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem64_RC128X()
340 return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem128_RC128X()
346 return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31); in isMem256_RC128X()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc232 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
438 X86::XMM0, X86::XMM1, X86::XMM2
603 X86::XMM0, X86::XMM1, X86::XMM2
880 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
904 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1173 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1237 X86::XMM0, X86::XMM1, X86::XMM2
1550 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1952 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1976 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
[all …]
DX86GenRegisterInfo.inc163 XMM0 = 143,
1279 { X86::XMM0 },
1586 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1636 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1956 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1986 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
2426 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
2436 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
2732 { 17U, X86::XMM0 },
2809 { 21U, X86::XMM0 },
[all …]
DX86GenGlobalISel.inc9493 … 7226:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, XMM0:{ *:[v4i32] }) => …
9495 GIR_AddRegister, /*InsnID*/1, X86::XMM0, /*AddRegisterRegFlags*/RegState::Define,
9496 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XMM0
DX86GenInstrInfo.inc16590 static const MCPhysReg ImplicitList21[] = { X86::XMM0, 0 };
16643 static const MCPhysReg ImplicitList74[] = { X86::XMM0, X86::EFLAGS, 0 };
16673 …86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XM…
16674 …86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XM…
DX86GenAsmMatcher.inc5302 MCK_XMM0, // register class 'XMM0'
7204 case X86::XMM0: OpKind = MCK_XMM0; break;
/third_party/libffi/src/x86/
Dwin64_intel.S67 movsd XMM0, qword ptr [RSP] ; movsd (%rsp), %xmm0
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h219 ENTRY(XMM0) \
DX86Disassembler.cpp1941 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp134 {codeview::RegisterId::XMM0, X86::XMM0}, in initLLVMToSEHAndCVRegMapping()
DX86InstComments.cpp207 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31) in getVectorRegSize()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def151 CV_REGISTER(XMM0, 154)