| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_bo.c | 63 size = align64(size, getpagesize()); in radv_amdgpu_bo_va_op()
357 p_atomic_add(&ws->allocated_vram, -align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_destroy()
359 p_atomic_add(&ws->allocated_vram_vis, -align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_destroy()
364 p_atomic_add(&ws->allocated_gtt, -align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_destroy()
534 p_atomic_add(&ws->allocated_vram, align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_create()
536 p_atomic_add(&ws->allocated_vram_vis, align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_create()
541 p_atomic_add(&ws->allocated_gtt, align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_create()
657 p_atomic_add(&ws->allocated_gtt, align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_from_ptr()
747 p_atomic_add(&ws->allocated_vram, align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_from_fd()
749 p_atomic_add(&ws->allocated_gtt, align64(bo->size, ws->info.gart_page_size)); in radv_amdgpu_winsys_bo_from_fd()
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| /third_party/mesa3d/src/util/ |
| D | blob.c | 88 const size_t new_size = align64(blob->size, alignment); in blob_align()
105 blob->current = blob->data + align64(blob->current - blob->data, alignment); in blob_reader_align()
215 assert(align64((_offset), (_align)) == (_offset)) in BLOB_WRITE_TYPE()
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| D | ralloc.c | 114 void *block = malloc(align64(size + sizeof(ralloc_header), in ralloc_size()
162 info = realloc(old, align64(size + sizeof(ralloc_header), in resize()
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| D | u_math.h | 708 align64(uint64_t value, unsigned alignment) in align64() function
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| /third_party/mesa3d/src/intel/common/ |
| D | intel_aux_map.c | 155 uint64_t aligned = align64(gpu, align); in align_and_verify_space()
457 assert(align64(address, INTEL_AUX_MAP_MAIN_PAGE_SIZE) == address); in intel_aux_map_add_mapping()
458 assert(align64(aux_address, INTEL_AUX_MAP_AUX_PAGE_SIZE) == aux_address); in intel_aux_map_add_mapping()
533 assert(align64(address, INTEL_AUX_MAP_MAIN_PAGE_SIZE) == address); in intel_aux_map_unmap_range()
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| /third_party/mesa3d/src/intel/tools/ |
| D | intel_sanitize_gpu.c | 168 .offset = align64(bo_size(fd, handle), 4096), in padding_is_good()
212 create->size = align64(original_size, 4096) + PADDING_SIZE; in create_with_padding()
222 .offset = align64(create->size, 4096), in create_with_padding()
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| /third_party/mesa3d/src/mapi/glapi/gen/ |
| D | glX_proto_recv.py | 241 align64 = 0
251 align64 = 1
297 if align64:
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 438 surf_ws->meta_offset = align64(surf_ws->total_size, 1 << surf_ws->meta_alignment_log2); in radeon_winsys_surface_init()
444 surf_ws->fmask_offset = align64(surf_ws->total_size, 1 << surf_ws->fmask_alignment_log2); in radeon_winsys_surface_init()
450 surf_ws->cmask_offset = align64(surf_ws->total_size, 1 << surf_ws->cmask_alignment_log2); in radeon_winsys_surface_init()
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| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_bo.c | 219 ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_destroy()
221 ws->allocated_gtt -= align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_destroy()
606 ws->allocated_vram += align64(size, ws->info.gart_page_size); in amdgpu_create_bo()
608 ws->allocated_gtt += align64(size, ws->info.gart_page_size); in amdgpu_create_bo()
1139 map_size = align64(size, RADEON_SPARSE_PAGE_SIZE); in amdgpu_bo_sparse_create()
1414 size = align64(size, ws->info.gart_page_size); in amdgpu_bo_create()
1565 ws->allocated_vram += align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_from_handle()
1567 ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_from_handle()
1673 uint64_t aligned_size = align64(size, ws->info.gart_page_size); in amdgpu_bo_from_ptr()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_sqtt.c | 45 data_offset = align64(sizeof(struct ac_thread_trace_info) * max_se, in ac_thread_trace_get_data_offset()
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| D | ac_surface.c | 695 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256; in gfx6_compute_level()
1376 surf->meta_size = align64(surf->surf_size >> 8, (1 << surf->meta_alignment_log2) * 4); in gfx6_compute_surface()
2514 surf->fmask_offset = align64(surf->total_size, 1 << surf->fmask_alignment_log2); in ac_compute_surface()
2521 surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2); in ac_compute_surface()
2539 …surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment… in ac_compute_surface()
2543 surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2); in ac_compute_surface()
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| D | ac_surface_modifier_test.c | 325 dcc_size = align64(dcc_size, dcc_align); in test_modifier()
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| D | ac_rtld.c | 155 total_size = align64(total_size, s->align); in layout_symbols()
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| /third_party/mesa3d/src/imagination/vulkan/ |
| D | pvr_job_render.c | 200 initial_size = align64(initial_size, size_alignment); in pvr_free_list_create()
201 max_size = align64(max_size, size_alignment); in pvr_free_list_create()
202 grow_size = align64(grow_size, size_alignment); in pvr_free_list_create()
209 assert(align64(max_size, size_alignment) == max_size); in pvr_free_list_create()
226 assert(align64(size, addr_alignment) == size); in pvr_free_list_create()
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| /third_party/mesa3d/src/nouveau/drm-shim/ |
| D | nouveau_noop.c | 81 nouveau.next_offset = align64(nouveau.next_offset, create->align); in nouveau_ioctl_gem_new()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_sqtt.c | 414 align64(device->thread_trace.buffer_size, 1u << SQTT_BUFFER_ALIGN_SHIFT); in radv_thread_trace_init_bo()
417 size = align64(sizeof(struct ac_thread_trace_info) * max_se, 1 << SQTT_BUFFER_ALIGN_SHIFT); in radv_thread_trace_init_bo()
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| D | radv_image.c | 1427 surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2); in radv_image_alloc_single_sample_cmask()
1693 align64(image->size, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
1911 image->size = align64(image->size, image->alignment); in radv_image_create()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.3.rst | 137 - radv: fix aligning the image offset by using align64()
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| /third_party/mesa3d/src/gallium/drivers/d3d12/ |
| D | d3d12_bufmgr.cpp | 326 size = align64(size, D3D12_CONSTANT_BUFFER_DATA_PLACEMENT_ALIGNMENT); in d3d12_bufmgr_create_buffer()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_sqtt.c | 50 sctx->thread_trace->buffer_size = align64(sctx->thread_trace->buffer_size, in si_thread_trace_init_bo()
54 size = align64(sizeof(struct ac_thread_trace_info) * max_se, in si_thread_trace_init_bo()
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| /third_party/mesa3d/src/virtio/vulkan/ |
| D | vn_buffer.c | 280 out->memory.memoryRequirements.size = align64( in vn_buffer_cache_get_memory_requirements()
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| D | vn_device_memory.c | 184 pool->used += align64(mem->size, pool_align); in vn_device_memory_pool_suballocate()
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| /third_party/mesa3d/src/vulkan/runtime/ |
| D | vk_pipeline_cache.c | 226 assert(blob->size == align64(blob->size, VK_PIPELINE_CACHE_BLOB_ALIGN)); in vk_pipeline_cache_object_serialize()
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| /third_party/mesa3d/src/gallium/drivers/zink/ |
| D | zink_bo.c | 269 … mai.allocationSize = align64(mai.allocationSize, screen->info.props.limits.minMemoryMapAlignment); in bo_create_internal()
635 size = align64(size, screen->info.props.limits.minMemoryMapAlignment); in zink_bo_create()
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| /third_party/mesa3d/src/gallium/drivers/llvmpipe/ |
| D | lp_texture.c | 153 total_size += align64(mipsize, mip_align); in llvmpipe_texture_layout()
|