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Searched refs:bank (Results 1 – 25 of 92) sorted by relevance

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/third_party/ltp/tools/sparse/sparse-src/
Ddominate.c28 struct piggy *bank; in bank_init() local
29 bank = calloc(1, sizeof(*bank) + levels * sizeof(bank->lists[0])); in bank_init()
30 bank->max = levels - 1; in bank_init()
31 return bank; in bank_init()
34 static void bank_free(struct piggy *bank, unsigned int levels) in bank_free() argument
37 free_ptr_list(&bank->lists[levels]); in bank_free()
38 free(bank); in bank_free()
41 static void bank_put(struct piggy *bank, struct basic_block *bb) in bank_put() argument
44 assert(level <= bank->max); in bank_put()
45 add_bb(&bank->lists[level], bb); in bank_put()
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/third_party/node/deps/undici/src/docs/best-practices/
Dmocking-request.md8 // bank.mjs
12 const { body } = await request('http://localhost:3000/bank-transfer',
34 import { bankTransfer } from './bank.mjs'
45 path: '/bank-transfer',
65 path: '/bank-transfer',
68 message: 'bank account not found'
73 assert.deepEqual(badRequest, { message: 'bank account not found' })
92 path: '/bank-transfer',
100 // MockNotMatchedError: Mock dispatch not matched for path '/bank-transfer':
110 path: '/bank-transfer',
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/third_party/mesa3d/src/imagination/rogue/
Drogue_encoders.c127 size_t bank, in rogue_encoder_reg() argument
133 assert(util_last_bit64(bank) <= bank_bits); in rogue_encoder_reg()
136 *value |= (bank << num_bits); in rogue_encoder_reg()
150 size_t bank; \
154 bank = va_arg(args, size_t); \
157 return rogue_encoder_reg(value, bank_bits, bank, num_bits, num); \
/third_party/mesa3d/src/amd/addrlib/src/r800/
Degbaddrlib.cpp1610 UINT_32 bank; in ComputeSurfaceAddrFromCoordMacroTiled() local
1805 bank = ComputeBankFromCoord(x, in ComputeSurfaceAddrFromCoordMacroTiled()
1831 UINT_32 bankBits = bank << (numPipeInterleaveBits + numPipeBits + in ComputeSurfaceAddrFromCoordMacroTiled()
2348 UINT_32 bank; in ComputeSurfaceCoordFromAddrMacroTiled() local
2445 bank = ComputeBankFromAddr(addr, banks, pipes); in ComputeSurfaceCoordFromAddrMacroTiled()
2452 bank, in ComputeSurfaceCoordFromAddrMacroTiled()
2476 UINT_32 bank, ///< [in] bank number in ComputeSurfaceCoord2DFromBankPipe() argument
2525 bank ^= tileSplitRotation * tileSlices; in ComputeSurfaceCoord2DFromBankPipe()
2528 bank ^= bankRotation * (slice / microTileThickness) + bankSwizzle; in ComputeSurfaceCoord2DFromBankPipe()
2529 bank %= pTileInfo->banks; in ComputeSurfaceCoord2DFromBankPipe()
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Degbaddrlib.h194 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0;
198 UINT_32 bank, UINT_32 pipe,
284 UINT_32 bank, UINT_32 pipe,
Dsiaddrlib.h230 UINT_32 bank, UINT_32 pipe,
236 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const;
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_instr.cpp355 int bank = u.kcache_bank(); in try_reserve_kcache() local
363 if (kcache[i].bank < bank) in try_reserve_kcache()
366 if ((kcache[i].bank == bank && in try_reserve_kcache()
368 kcache[i].bank > bank) { in try_reserve_kcache()
374 kcache[i].bank = bank; in try_reserve_kcache()
404 kcache[i].bank = bank; in try_reserve_kcache()
/third_party/node/deps/brotli/c/enc/
Dhash_forgetful_chain_inc.h138 const size_t bank = key & (NUM_BANKS - 1); in FN() local
139 const size_t idx = self->free_slot_idx[bank]++ & (BANK_SIZE - 1); in FN()
143 banks[bank].slots[idx].delta = (uint16_t)delta; in FN()
144 banks[bank].slots[idx].next = head[key]; in FN()
243 const size_t bank = key & (NUM_BANKS - 1); in FN() local
254 slot = banks[bank].slots[last].next; in FN()
255 delta = banks[bank].slots[last].delta; in FN()
/third_party/skia/third_party/externals/brotli/c/enc/
Dhash_forgetful_chain_inc.h138 const size_t bank = key & (NUM_BANKS - 1); in FN() local
139 const size_t idx = self->free_slot_idx[bank]++ & (BANK_SIZE - 1); in FN()
143 banks[bank].slots[idx].delta = (uint16_t)delta; in FN()
144 banks[bank].slots[idx].next = head[key]; in FN()
243 const size_t bank = key & (NUM_BANKS - 1); in FN() local
254 slot = banks[bank].slots[last].next; in FN()
255 delta = banks[bank].slots[last].delta; in FN()
/third_party/alsa-lib/src/seq/
Dseq_old.c154 int bank ATTRIBUTE_UNUSED, in snd_instr_iwffff_open_rom()
162 int bank ATTRIBUTE_UNUSED, in snd_instr_iwffff_open_rom_file()
179 int bank ATTRIBUTE_UNUSED, in snd_instr_iwffff_load()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUGenRegisterBankInfo.def172 default: llvm_unreachable("Invalid register bank");
186 default: llvm_unreachable("Invalid register bank");
232 /* FIXME: The generic register bank select does not support complex
235 * FIXME: register bank select now tries to handle complex break downs,
262 // the register bank is SGPR or if we don't know how to handle the vector
/third_party/mesa3d/src/freedreno/.gitlab-ci/reference/
Dcrash.log3392 - bank: 0
3394 - bank: 1
3396 - bank: 2
3399 - bank: 0
3401 - bank: 1
3403 - bank: 2
3406 - bank: 0
3408 - bank: 1
3410 - bank: 2
3413 - bank: 0
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/third_party/mesa3d/src/gallium/drivers/r300/
Dr300_fs.c303 unsigned int bank = 0; in r300_emit_fs_code_to_buffer() local
340 unsigned int bank_alu_offset = bank * 64; in r300_emit_fs_code_to_buffer()
342 unsigned int bank_tex_offset = bank * 32; in r300_emit_fs_code_to_buffer()
346 (bank << R400_BANK_SHIFT) | R400_R390_MODE_ENABLE : 0);//2 in r300_emit_fs_code_to_buffer()
380 bank++; in r300_emit_fs_code_to_buffer()
/third_party/mesa3d/src/gallium/drivers/r600/
Deg_asm.c50 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK2(cf->kcache[2].bank) | in eg_bytecode_cf_build()
51 S_SQ_CF_ALU_WORD0_EXT_KCACHE_BANK3(cf->kcache[3].bank) | in eg_bytecode_cf_build()
63 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) | in eg_bytecode_cf_build()
64 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank); in eg_bytecode_cf_build()
Dr600_asm.c1012 unsigned bank, unsigned line, unsigned index_mode) in r600_bytecode_alloc_kcache_line() argument
1020 if (kcache[i].bank < bank) in r600_bytecode_alloc_kcache_line()
1023 if ((kcache[i].bank == bank && kcache[i].addr > line+1) || in r600_bytecode_alloc_kcache_line()
1024 kcache[i].bank > bank) { in r600_bytecode_alloc_kcache_line()
1033 kcache[i].bank = bank; in r600_bytecode_alloc_kcache_line()
1063 kcache[i].bank = bank; in r600_bytecode_alloc_kcache_line()
1079 unsigned bank, line, sel = alu->src[i].sel, index_mode; in r600_bytecode_alloc_inst_kcache_lines() local
1084 bank = alu->src[i].kc_bank; in r600_bytecode_alloc_inst_kcache_lines()
1085 assert(bank < R600_MAX_HW_CONST_BUFFERS); in r600_bytecode_alloc_inst_kcache_lines()
1089 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode))) in r600_bytecode_alloc_inst_kcache_lines()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/GlobalISel/
DRegisterBank.td1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
/third_party/alsa-lib/include/sound/uapi/
Dasound_fm.h128 unsigned char bank; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def73 // Cross register bank copies.
217 assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
218 assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
/third_party/vixl/src/aarch64/
Dregisters-aarch64.h522 inline static unsigned GetMaxCodeFor(CPURegister::RegisterBank bank);
534 RegisterBank bank,
538 bank_(bank), in code_()
947 unsigned CPURegister::GetMaxCodeFor(CPURegister::RegisterBank bank) { in GetMaxCodeFor() argument
948 switch (bank) { in GetMaxCodeFor()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DCMakeLists.txt12 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DCMakeLists.txt13 tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DCMakeLists.txt13 tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
/third_party/ltp/testcases/kernel/mce-test/tsrc/erst-inj/
Dcper.h197 __u16 bank; member
/third_party/mesa3d/src/freedreno/afuc/
DREADME.rst17 them; any global state like which bank of context registers is to
214 arranged so bit 11 is zero for bank 0 and 1 for bank 1. The ME fw (at
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_builder.cpp214 .KCACHE_BANK2(bc.kc[2].bank) in build_cf_alu()
215 .KCACHE_BANK3(bc.kc[3].bank) in build_cf_alu()
232 .KCACHE_BANK0(bc.kc[0].bank) in build_cf_alu()
233 .KCACHE_BANK1(bc.kc[1].bank) in build_cf_alu()

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