| /third_party/mesa3d/src/util/ |
| D | register_allocate.h | 62 unsigned int base_reg, unsigned int reg);
66 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
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| D | register_allocate.c | 160 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
162 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
164 util_dynarray_foreach(®s->regs[base_reg].conflict_list, unsigned int, in ra_add_transitive_reg_conflict()
179 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict() argument
181 ra_add_reg_conflict(regs, reg0, base_reg); in ra_add_transitive_reg_pair_conflict()
182 ra_add_reg_conflict(regs, reg1, base_reg); in ra_add_transitive_reg_pair_conflict()
184 util_dynarray_foreach(®s->regs[base_reg].conflict_list, unsigned int, i) { in ra_add_transitive_reg_pair_conflict()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_spill.c | 128 struct ir3_register *base_reg; member
164 ctx->base_reg = mov->dsts[0]; in add_base_reg()
170 ctx->limit_pressure.full -= reg_size(ctx->base_reg); in add_base_reg()
746 ir3_src_create(spill, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in spill()
920 ir3_src_create(reload, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in reload()
1841 instr->dsts[0] == ctx->base_reg) in handle_block()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_cmd_buffer.c | 990 uint32_t base_reg = pipeline->user_data_0[stage]; in radv_emit_userdata_address() local
996 radv_emit_shader_pointer(device, cs, base_reg + loc->sgpr_idx * 4, va, false); in radv_emit_userdata_address()
1211 uint32_t base_reg = pipeline->user_data_0[stage]; in radv_emit_inline_push_consts() local
1217 radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs); in radv_emit_inline_push_consts()
3299 uint32_t base_reg = cmd_buffer->state.graphics_pipeline->base.user_data_0[MESA_SHADER_VERTEX]; in emit_prolog_inputs() local
3302 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in emit_prolog_inputs()
3890 uint32_t base_reg; in radv_emit_streamout_buffers() local
3900 base_reg = pipeline->base.user_data_0[stage]; in radv_emit_streamout_buffers()
3902 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va, in radv_emit_streamout_buffers()
3909 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0; in radv_emit_streamout_buffers()
[all …]
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| /third_party/node/deps/v8/src/diagnostics/x64/ |
| D | disasm-x64.cc | 346 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } in base_reg() function in disasm::DisassemblerX64
2394 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
2399 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
2421 NameOfCPURegister(base_reg(current & 0x07)), in InstructionDecode()
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| /third_party/node/deps/v8/src/builtins/x64/ |
| D | builtins-x64.cc | 4492 Register base_reg = r15; in CallApiFunctionAndReturn() local
4493 __ Move(base_reg, next_address); in CallApiFunctionAndReturn()
4494 __ movq(prev_next_address_reg, Operand(base_reg, kNextOffset)); in CallApiFunctionAndReturn()
4495 __ movq(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
4496 __ addl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
4527 __ subl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
4528 __ movq(Operand(base_reg, kNextOffset), prev_next_address_reg); in CallApiFunctionAndReturn()
4529 __ cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
4602 __ movq(Operand(base_reg, kLimitOffset), prev_limit_reg); in CallApiFunctionAndReturn()
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| /third_party/mesa3d/src/freedreno/decode/ |
| D | cffdec.c | 1457 const unsigned base_reg = stage == MESA_SHADER_COMPUTE in cp_load_state() local
1462 const unsigned reg = base_reg + (dwords[1] >> 28) * 2; in cp_load_state()
1466 const unsigned reg = base_reg + (dwords[1] >> 28); in cp_load_state()
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| /third_party/mesa3d/src/microsoft/vulkan/ |
| D | dzn_private.h | 660 uint32_t *base_reg; member
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| D | dzn_pipeline.c | 294 binding = layout->binding_translation[set].base_reg[binding]; in adjust_resource_index_binding()
325 var->data.binding = layout->binding_translation[s].base_reg[b]; in adjust_var_bindings()
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| D | dzn_descriptor_set.c | 578 layout->binding_translation[s].base_reg = binding_translation; in dzn_pipeline_layout_create()
591 uint32_t *binding_trans = layout->binding_translation[j].base_reg; in dzn_pipeline_layout_create()
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| /third_party/node/deps/v8/src/interpreter/ |
| D | interpreter-assembler.cc | 263 TNode<IntPtrT> base_reg = RegisterLocation(BytecodeOperandReg(operand_index)); in GetRegisterListAtOperandIndex() local
265 return RegListNodePair(base_reg, reg_count); in GetRegisterListAtOperandIndex()
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| /third_party/pcre2/pcre2/src/ |
| D | pcre2_jit_simd_inc.h | 1142 sljit_s32 base_reg, sljit_s32 index_reg) in load_from_mem_vector() argument
1147 instruction[1] = (sljit_u16)(base_reg << 12); in load_from_mem_vector()
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| D | pcre2_jit_compile.c | 2613 int from_sp, base_reg, offset, i; in copy_recurse_data() local
2626 base_reg = STACK_TOP; in copy_recurse_data()
2633 base_reg = STACK_TOP; in copy_recurse_data()
2639 base_reg = TMP2; in copy_recurse_data()
2649 if (base_reg != TMP2) in copy_recurse_data()
2676 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, common->recursive_head_ptr); in copy_recurse_data()
2679 delayed_mem_copy_move(&status, SLJIT_SP, common->recursive_head_ptr, base_reg, stackptr); in copy_recurse_data()
2688 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, common->control_head_ptr); in copy_recurse_data()
2691 delayed_mem_copy_move(&status, SLJIT_SP, common->control_head_ptr, base_reg, stackptr); in copy_recurse_data()
2980 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, private_srcw[i]); in copy_recurse_data()
[all …]
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| D | code-generator-riscv64.cc | 888 Register base_reg = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
889 __ Add64(i.OutputRegister(), base_reg, Operand(offset.offset())); in AssembleArchInstruction()
902 __ Add64(kScratchReg, base_reg, Operand(offset.offset())); in AssembleArchInstruction()
909 __ Add64(kScratchReg, base_reg, Operand(offset.offset())); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/codegen/x64/ |
| D | assembler-x64.cc | 177 int base_reg = (has_sib ? operand.data().buf[1] : modrm) & 0x07; in Operand() local
180 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base. in Operand()
202 } else if (disp_value != 0 || (base_reg == 0x05)) { in Operand()
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| /third_party/node/deps/v8/src/compiler/backend/loong64/ |
| D | code-generator-loong64.cc | 856 Register base_reg = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
857 __ Add_d(i.OutputRegister(), base_reg, Operand(offset.offset())); in AssembleArchInstruction()
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_32.c | 1024 #define EMIT_DATA_TRANSFER(type, add, target_reg, base_reg, arg) \ argument
1025 …(data_transfer_insts[(type) & 0xf] | ((add) << 23) | RD(target_reg) | RN(base_reg) | (sljit_uw)(ar…
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| D | code-generator-mips.cc | 904 Register base_reg = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
905 __ Addu(i.OutputRegister(), base_reg, Operand(offset.offset())); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| D | code-generator-mips64.cc | 865 Register base_reg = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
866 __ Daddu(i.OutputRegister(), base_reg, Operand(offset.offset())); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/execution/s390/ |
| D | simulator-s390.cc | 2982 #define GET_ADDRESS(index_reg, base_reg, offset) \ argument
2984 (((base_reg) == 0) ? 0 : get_register(base_reg)) + offset
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