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Searched refs:buildCopy (Results 1 – 18 of 18) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp112 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
146 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
274 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg); in assignValueToReg()
279 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
285 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
DX86AvoidStoreForwardingBlocks.cpp108 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
384 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
445 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
456 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
466 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
476 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
486 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp76 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
81 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP)); in getStackAddress()
173 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
366 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
412 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
888 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1014 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
DAArch64InstructionSelector.cpp626 auto Copy = MIB.buildCopy({From}, {SrcReg}); in selectSubregisterCopy()
1652 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
2489 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0)); in selectTLSGlobalValue()
2771 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
4107 MIRBuilder.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
4125 MIRBuilder.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
4778 auto Copy = MIB.buildCopy({NarrowReg}, {ExtReg}); in narrowExtendRegIfNeeded()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp62 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
101 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
110 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
115 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
331 B.buildCopy(ReturnAddrVReg, LiveInReturn); in lowerReturn()
416 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
596 B.buildCopy(LiveInReturn, ReturnAddrReg); in lowerFormalArguments()
DAMDGPULegalizerInfo.cpp1868 B.buildCopy(DstReg, LiveIn); in loadInputValue()
1880 B.buildCopy(LiveIn, Arg->getRegister()); in loadInputValue()
DAMDGPURegisterBankInfo.cpp1500 auto Copy = B.buildCopy(LLT::scalar(1), SrcReg); in applyMappingImpl()
1837 B.buildCopy(DefRegs[1], DefRegs[0]); in applyMappingImpl()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp168 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
173 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
282 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
295 MIRBuilder.buildCopy(SPReg, Register(Mips::SP)); in getStackAddress()
522 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); in lowerFormalArguments()
632 MIRBuilder.buildCopy( in lowerCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP)); in getStackAddress()
124 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
350 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
359 MIRBuilder.buildCopy(PhysRegToVReg, PhysReg); in assignValueToReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DIRTranslator.cpp349 MIRBuilder.buildCopy( in translateCompare()
352 MIRBuilder.buildCopy( in translateCompare()
881 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
926 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1036 MIRBuilder.buildCopy(Regs[0], SrcReg); in translateBitCast()
1119 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1485 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
1499 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
1572 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallSite()
1787 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
DCSEMIRBuilder.cpp132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg()); in generateCopiesIfRequired()
DCombinerHelper.cpp49 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
284 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
DCallLowering.cpp342 MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0)); in handleAssignments()
DMachineIRBuilder.cpp273 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
487 return buildCopy(Dst, Src); in buildCast()
DLegalizerHelper.cpp714 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0)); in narrowScalar()
4218 MIRBuilder.buildCopy(DstReg, Val); in lowerShuffleVector()
4265 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in lowerDynStackAlloc()
4280 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
4281 MIRBuilder.buildCopy(Dst, SPTmp); in lowerDynStackAlloc()
4486 MIRBuilder.buildCopy(Dst, Reg); in lowerReadRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DSplitKit.h434 SlotIndex buildCopy(unsigned FromReg, unsigned ToReg, LaneBitmask LaneMask,
DSplitKit.cpp538 SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg, in buildCopy() function in SplitEditor
666 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h709 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);