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Searched refs:buildZExt (Results 1 – 8 of 8) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp831 MIRBuilder.buildZExt(DstReg, TmpReg); in narrowScalar()
1199 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); in widenScalarMergeValues()
1207 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalarMergeValues()
1318 auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg); in widenScalarUnmergeValues()
1484 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalar()
2150 MIRBuilder.buildZExt(DstReg, TmpReg); in lower()
2234 MIRBuilder.buildZExt(ZExtCarryIn, CarryIn); in lower()
2266 MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn); in lower()
3440 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); in multiplyRegisters()
3445 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); in multiplyRegisters()
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DCallLowering.cpp481 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
DMachineIRBuilder.cpp419 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res, in buildZExt() function in MachineIRBuilder
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp1552 B.buildZExt(NewSrcReg, MI.getOperand(4).getReg()); in applyMappingImpl()
1580 B.buildZExt(NewCondReg, CondRegs[0]); in applyMappingImpl()
1632 B.buildZExt(NewCondReg, CondReg); in applyMappingImpl()
1900 ZextLo = B.buildZExt(S32, Lo).getReg(0); in applyMappingImpl()
1903 Register ZextHi = B.buildZExt(S32, Hi).getReg(0); in applyMappingImpl()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64LegalizerInfo.cpp679 auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg); in legalizeShlAshrLshr()
DAArch64CallLowering.cpp296 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0); in lowerReturn()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp332 MIRBuilder.buildZExt(ExtReg, ValReg); in extendRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h569 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);