| /third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| D | fd3_program.c | 259 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in fd3_program_emit()
263 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in fd3_program_emit()
366 unsigned compmask = fp->inputs[j].compmask; in fd3_program_emit() local
375 if (compmask & (1 << i)) { in fd3_program_emit()
392 if (compmask & 0x1) { in fd3_program_emit()
396 if (compmask & 0x2) { in fd3_program_emit()
400 if (compmask & 0x4) { in fd3_program_emit()
405 if (compmask & 0x8) { in fd3_program_emit()
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| D | fd3_emit.c | 389 if (!vp->inputs[i].compmask) in fd3_emit_vertex_bufs()
413 if (vp->inputs[i].compmask) { in fd3_emit_vertex_bufs()
443 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) | in fd3_emit_vertex_bufs()
452 total_in += util_bitcount(vp->inputs[i].compmask); in fd3_emit_vertex_bufs()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_shader.h | 624 uint8_t compmask; member
999 if (so->inputs[i].compmask && so->inputs[i].bary) in ir3_next_varying()
1022 uint8_t compmask; member
1038 uint8_t compmask, uint8_t loc) in ir3_link_add() argument
1040 for (int j = 0; j < util_last_bit(compmask); j++) { in ir3_link_add()
1045 l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask)); in ir3_link_add()
1053 l->var[i].compmask = compmask; in ir3_link_add()
1107 fs->inputs[j].compmask, fs->inputs[j].inloc); in ir3_link_shaders()
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| D | ir3_shader.c | 80 if (v->inputs[i].compmask) { in fixup_regfootprint()
81 unsigned n = util_last_bit(v->inputs[i].compmask) - 1; in fixup_regfootprint()
844 so->inputs[i].compmask, so->inputs[i].inloc, so->inputs[i].bary); in ir3_shader_disasm()
938 unsigned compmask = in ir3_link_stream_out() local
958 compmask, nextloc); in ir3_link_stream_out()
964 if (compmask & ~l->var[idx].compmask) { in ir3_link_stream_out()
965 l->var[idx].compmask |= compmask; in ir3_link_stream_out()
967 l->max_loc, l->var[idx].loc + util_last_bit(l->var[idx].compmask)); in ir3_link_stream_out()
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| D | ir3_compiler_nir.c | 64 create_input(struct ir3_context *ctx, unsigned compmask) in create_input() argument
70 __ssa_dst(in)->wrmask = compmask; in create_input()
1728 unsigned compmask, struct ir3_instruction *instr) in add_sysval_input_compmask() argument
1739 so->inputs[n].compmask = compmask; in add_sysval_input_compmask()
1742 so->sysval_in += util_last_bit(compmask); in add_sysval_input_compmask()
1747 unsigned compmask) in create_sysval_input() argument
1749 assert(compmask); in create_sysval_input()
1750 struct ir3_instruction *sysval = create_input(ctx, compmask); in create_sysval_input()
1751 add_sysval_input_compmask(ctx, slot, compmask, sysval); in create_sysval_input()
3926 unsigned compmask; in setup_input() local
[all …]
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| D | ir3_parser.y | 230 static void add_sysval(unsigned reg, unsigned compmask, gl_system_value sysval) in add_sysval() argument
236 variant->inputs[n].compmask = compmask; in add_sysval()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| D | fd4_program.c | 324 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in fd4_program_emit()
328 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in fd4_program_emit()
506 unsigned compmask = s[FS].v->inputs[j].compmask; in fd4_program_emit() local
515 if (compmask & (1 << i)) { in fd4_program_emit()
533 if (compmask & 0x1) { in fd4_program_emit()
537 if (compmask & 0x2) { in fd4_program_emit()
541 if (compmask & 0x4) { in fd4_program_emit()
546 if (compmask & 0x8) { in fd4_program_emit()
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| D | fd4_emit.c | 534 if (!vp->inputs[i].compmask) in fd4_emit_vertex_bufs()
558 if (vp->inputs[i].compmask) { in fd4_emit_vertex_bufs()
588 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) | in fd4_emit_vertex_bufs()
597 total_in += util_bitcount(vp->inputs[i].compmask); in fd4_emit_vertex_bufs()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_program.c | 461 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in fd5_program_emit()
465 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in fd5_program_emit()
640 unsigned compmask = s[FS].v->inputs[j].compmask; in fd5_program_emit() local
649 if (compmask & (1 << i)) { in fd5_program_emit()
667 if (compmask & 0x1) { in fd5_program_emit()
671 if (compmask & 0x2) { in fd5_program_emit()
675 if (compmask & 0x4) { in fd5_program_emit()
680 if (compmask & 0x8) { in fd5_program_emit()
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| D | fd5_emit.c | 481 if (vp->inputs[i].compmask) { in fd5_emit_vertex_bufs()
512 A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) | in fd5_emit_vertex_bufs()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_program.c | 665 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); in setup_stateobj()
669 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); in setup_stateobj()
1094 assert(vs->inputs[i].compmask); in setup_stateobj()
1096 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) | in setup_stateobj()
1176 unsigned compmask = fs->inputs[j].compmask; in emit_interp_state() local
1184 if (compmask & (1 << i)) { in emit_interp_state()
1200 if (compmask & 0x1) { in emit_interp_state()
1204 if (compmask & 0x2) { in emit_interp_state()
1208 if (compmask & 0x4) { in emit_interp_state()
1213 if (compmask & 0x8) { in emit_interp_state()
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | tu_pipeline.c | 1122 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask); in tu6_emit_vpc()
1319 const uint32_t compmask = fs->inputs[index].compmask; in tu6_vpc_varying_mode() local
1328 if (compmask & 0x1) { in tu6_vpc_varying_mode()
1332 if (compmask & 0x2) { in tu6_vpc_varying_mode()
1336 if (compmask & 0x4) { in tu6_vpc_varying_mode()
1340 if (compmask & 0x8) { in tu6_vpc_varying_mode()
1346 if (compmask & (1 << i)) { in tu6_vpc_varying_mode()
1903 .writemask = vs->inputs[input_idx].compmask, in tu6_emit_vertex_input()
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