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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME_P9.txt176 . (set f128:$vT, (fcopysign f128:$vB, f128:$vA)
180 . (set f128:$vT, (fabs f128:$vB)) // xsabsqp
181 (set f128:$vT, (fneg (fabs f128:$vB))) // xsnabsqp
182 (set f128:$vT, (fneg f128:$vB)) // xsnegqp
188 (set f128:$vT, (fadd f128:$vA, f128:$vB)) // xsaddqp
189 (set f128:$vT, (fmul f128:$vA, f128:$vB)) // xsmulqp
192 (set f128:$vT, (fdiv f128:$vA, f128:$vB)) // xsdivqp
193 (set f128:$vT, (fsub f128:$vA, f128:$vB)) // xssubqp
194 (set f128:$vT, (fsqrt f128:$vB))) // xssqrtqp
213 (set f128:$vT, (PPCfaddrto f128:$vA, f128:$vB)) // xsaddqpo
[all …]
DPPCInstrVSX.td1076 def : Pat<(v2i64 (bitconvert f128:$A)),
1078 def : Pat<(v4i32 (bitconvert f128:$A)),
1080 def : Pat<(v8i16 (bitconvert f128:$A)),
1082 def : Pat<(v16i8 (bitconvert f128:$A)),
2658 [(set f128:$vT,
2659 (fcopysign f128:$vB, f128:$vA))]>;
2663 [(set f128:$vT, (fabs f128:$vB))]>;
2665 [(set f128:$vT, (fneg (fabs f128:$vB)))]>;
2667 [(set f128:$vT, (fneg f128:$vB))]>;
2675 [(set f128:$vT, (fadd f128:$vA, f128:$vB))]>;
[all …]
DPPCCallingConv.td62 CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2]>>>,
96 // For P9, f128 are passed in vector registers.
97 CCIfType<[f128],
158 CCIfType<[f128],
231 CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToStack<16, 16>>>
256 CCIfType<[f128],
DPPCInstrInfo.td1366 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>;
3797 // Instantiations of CRNotPat for f128.
3798 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)),
3800 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)),
3802 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)),
3804 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)),
3806 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)),
3808 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)),
3810 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)),
3847 // SETCC for f128.
[all …]
/third_party/libffi/src/powerpc/
Dffi_linux64.c450 float128 *f128; in ffi_prep_args64() member
490 float128 **f128; in ffi_prep_args64() member
510 vec_base.f128 -= NUM_VEC_ARG_REGISTERS64; in ffi_prep_args64()
550 *vec_base.f128++ = **p_argv.f128; in ffi_prep_args64()
552 *next_arg.f128 = **p_argv.f128; in ffi_prep_args64()
553 if (++next_arg.f128 == gpr_end.f128) in ffi_prep_args64()
554 next_arg.f128 = rest.f128; in ffi_prep_args64()
671 float128 *f128; in ffi_prep_args64() member
683 *vec_base.f128++ = *arg.f128++; in ffi_prep_args64()
685 *next_arg.f128 = *arg.f128++; in ffi_prep_args64()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td359 // Extra selection patterns for f128, f128mem
363 def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
365 def : Pat<(store (f128 VR128:$src), addr:$dst),
375 def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
377 def : Pat<(store (f128 VR128:$src), addr:$dst),
387 def : Pat<(alignedstore (f128 VR128X:$src), addr:$dst),
389 def : Pat<(store (f128 VR128X:$src), addr:$dst),
400 def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
403 def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
406 def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))),
[all …]
DX86CallingConv.td102 CCIfType<[f32, f64, f128],
139 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
183 CCIfType<[f32, f64, f128],
322 CCIfType<[f32, f64, f128],
334 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,
360 CCIfType<[f32, f64, f128],
400 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
542 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
567 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc1904 /* 4294*/ OPC_CheckChild1Type, MVT::f128,
1918 …// Src: (st f128:{ *:[f128] }:$rS, iaddrX16:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Pr…
1919 …// Dst: (STXV (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[f128] }:$rS, VSRC:{ *:[i32] }), memrix16:{ *:…
1930 …// Src: (st f128:{ *:[f128] }:$rS, xoaddr:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Pred…
1931 …// Dst: (STXVX (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[f128] }:$rS, VSRC:{ *:[i32] }), xoaddr:{ *:[…
2337 /* 5132*/ OPC_CheckChild0Type, MVT::f128,
2347 MVT::f128, 1/*#Ops*/, 1, // Results = #5
2353 …rc: (PPCstore_scal_int_from_vsr (PPCcv_fp_to_sint_in_vsr:{ *:[f64] } f128:{ *:[f128] }:$src), iadd…
2354 …// Dst: (STXSD (COPY_TO_REGCLASS:{ *:[f64] } (XSCVQPSDZ:{ *:[f128] } f128:{ *:[f128] }:$src), VFRC…
2359 MVT::f128, 1/*#Ops*/, 1, // Results = #5
[all …]
DPPCGenCallingConv.inc77 if (LocVT == MVT::f128) {
275 if (LocVT == MVT::f128) {
490 if (LocVT == MVT::f128) {
638 if (LocVT == MVT::f128) {
750 if (LocVT == MVT::f128) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td24 def SelectF128 : SelectWrapper<f128, FP128>;
26 def SelectVR128 : SelectWrapper<f128, VR128>;
97 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))),
100 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))),
110 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))),
113 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))),
133 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
205 def : Pat<(f128 (any_fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>;
206 def : Pat<(f128 (any_fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>;
216 def : Pat<(f128 (any_extloadf32 bdxaddr12only:$src)),
[all …]
DSystemZInstrVector.td1149 def : Pat<(f128 (any_fpextend (f32 VR32:$src))),
1171 def : Pat<(f32 (any_fpround (f128 VR128:$src))),
1490 def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>;
1497 def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>;
1504 def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>;
1511 def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>;
1518 def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>;
1525 def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>;
1527 def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>;
1528 def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>;
[all …]
DSystemZRegisterInfo.td219 defm FP128 : SystemZRegClass<"FP128", [f128], 128,
262 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128],
285 def v128xb : TypedReg<f128, VR128>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp109 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
114 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
115 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
128 else if (LocVT == MVT::f128 && Offset < 16*8) in CC_Sparc64_Full()
512 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
1053 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1076 assert(ValTy == MVT::f128 && "Unexpected type!"); in fixupVariableFloatArgs()
1159 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1166 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1426 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
[all …]
DSparcInstrInfo.td468 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
489 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
516 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
571 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
1147 [(set f128:$rd, (fpextend f32:$rs2))]>,
1157 [(set f128:$rd, (fpextend f64:$rs2))]>,
1162 [(set f32:$rd, (fpround f128:$rs2))]>,
1167 [(set f64:$rd, (fpround f128:$rs2))]>,
1203 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1222 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
[all …]
DSparcISelLowering.h195 return VT != MVT::f128; in ShouldShrinkFPConstant()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp227 if (RetVT == MVT::f128) in getFPEXT()
232 if (RetVT == MVT::f128) in getFPEXT()
237 if (RetVT == MVT::f128) in getFPEXT()
254 if (OpVT == MVT::f128) in getFPROUND()
263 if (OpVT == MVT::f128) in getFPROUND()
270 if (OpVT == MVT::f128) in getFPROUND()
275 if (OpVT == MVT::f128) in getFPROUND()
306 } else if (OpVT == MVT::f128) { in getFPTOSINT()
348 } else if (OpVT == MVT::f128) { in getFPTOUINT()
376 if (RetVT == MVT::f128) in getSINTTOFP()
[all …]
DValueTypes.cpp156 case MVT::f128: return Type::getFP128Ty(Context); in getTypeForEVT()
338 case Type::FP128TyID: return MVT(MVT::f128); in getVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallingConv.td49 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
54 // For hard-float, f128 values are returned as a pair of f64's rather than a
189 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
195 // whether the result was originally an f128 into the tablegen-erated code.
197 // f128 should only occur for the N64 ABI where long double is 128-bit. On
326 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
327 // f128 is not legal and is lowered to i128 which is further lowered to a pair
332 // whether the argument was originally an f128 into the tablegen-erated code.
334 // f128 should only occur for the N64 ABI where long double is 128-bit. On
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td39 CCBitConvertToType<f128>>>,
112 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
120 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
138 CCBitConvertToType<f128>>>,
154 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
189 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
252 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
274 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
348 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType<v2f64>>,
DAArch64CallingConvention.cpp99 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
DAArch64ISelLowering.cpp142 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
258 setOperationAction(ISD::FABS, MVT::f128, Expand); in AArch64TargetLowering()
259 setOperationAction(ISD::FADD, MVT::f128, Custom); in AArch64TargetLowering()
260 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
261 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
262 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
263 setOperationAction(ISD::FMA, MVT::f128, Expand); in AArch64TargetLowering()
264 setOperationAction(ISD::FMUL, MVT::f128, Custom); in AArch64TargetLowering()
265 setOperationAction(ISD::FNEG, MVT::f128, Expand); in AArch64TargetLowering()
266 setOperationAction(ISD::FPOW, MVT::f128, Expand); in AArch64TargetLowering()
[all …]
DAArch64InstrInfo.td2051 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>;
2232 [(set (f128 FPR128Op:$Rt),
2308 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2408 [(set (f128 FPR128Op:$Rt), (load (AArch64adr alignedglobal:$label)))]>;
2444 [(set (f128 FPR128Op:$Rt),
2747 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>;
2750 def : Pat<(store (f128 FPR128:$Rt),
2754 def : Pat<(store (f128 FPR128:$Rt),
2906 def : Pat<(store (f128 FPR128:$Rt),
2988 [(store (f128 FPR128Op:$Rt),
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc80 LocVT = MVT::f128;
324 if (LocVT == MVT::f128 ||
371 if (LocVT == MVT::f128 ||
404 LocVT == MVT::f128) {
659 LocVT == MVT::f128) {
748 LocVT == MVT::f128) {
837 LocVT == MVT::f128) {
1036 LocVT = MVT::f128;
1137 if (LocVT == MVT::f128 ||
DAArch64GenGlobalISel.inc7038 … *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, …
7078 … *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, …
7141 …m)) => (RSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7181 …) => (SQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7221 … => (SQRSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7261 …)) => (SQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7301 …) => (SQSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7341 …) => (UQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7381 …)) => (UQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
7416 …m)) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), …
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h54 f128 = 12, // This is a 128 bit floating point value enumerator
755 case f128: in getSizeInBits()
895 return MVT::f128; in getFloatingPointVT()

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