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Searched refs:getNumAllocatableRegs (Results 1 – 5 of 5) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterClassInfo.cpp149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
191 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC); in computePSetLimit()
DRegAllocGreedy.cpp922 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
923 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
2075 return RCI.getNumAllocatableRegs(ConstrainedRC); in getNumAllocatableRegsForConstraints()
2107 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
DMachineScheduler.cpp2760 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNSchedStrategy.cpp45 ->getNumAllocatableRegs(&AMDGPU::SGPR_32RegClass) - ErrorMargin; in initialize()
47 ->getNumAllocatableRegs(&AMDGPU::VGPR_32RegClass) - ErrorMargin; in initialize()