Searched refs:getOpRegClass (Results 1 – 5 of 5) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIAddIMGInit.cpp | 127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction() 133 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction() 151 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
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D | SIFixSGPRCopies.cpp | 665 if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction() 795 TII->getOpRegClass(*UseMI, UseMI->getOperandNo(&Use)); in processPHINode()
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D | SIInstrInfo.cpp | 303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandWithOffset() 307 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandWithOffset() 3424 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction() 3678 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx); in verifyInstruction() 3816 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo 4566 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands() 4569 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands() 4572 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands() 4576 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands() 4606 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands() [all …]
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D | SIInstrInfo.h | 804 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI, 834 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
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D | SIInsertWaitcnts.cpp | 498 const TargetRegisterClass *RC = TII->getOpRegClass(MIA, OpNo); in getRegInterval()
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