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Searched refs:getWavefrontSize (Results 1 – 17 of 17) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp527 .addImm(StackSize * ST.getWavefrontSize()); in emitEntryFunctionPrologue()
789 .addImm((Alignment - 1) * ST.getWavefrontSize()) in emitPrologue()
793 .addImm(-Alignment * ST.getWavefrontSize()) in emitPrologue()
809 .addImm(RoundedSize * ST.getWavefrontSize()) in emitPrologue()
844 .addImm(RoundedSize * ST.getWavefrontSize()) in emitEpilogue()
1117 .addImm(Amount * ST.getWavefrontSize()); in eliminateCallFramePseudoInstr()
DSIMachineFunctionInfo.cpp255 unsigned WaveSize = ST.getWavefrontSize(); in haveFreeLanesForSGPRSpill()
272 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPR()
DAMDGPUAtomicOptimizer.cpp449 Type *const WaveTy = B.getIntNTy(ST->getWavefrontSize()); in optimizeAtomic()
493 Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1); in optimizeAtomic()
DR600ControlFlowFinalizer.cpp111 if (ST->getWavefrontSize() == 64) { in requiresWorkAroundForInst()
122 assert(ST->getWavefrontSize() == 32); in requiresWorkAroundForInst()
DAMDGPUHSAMetadataStreamer.cpp228 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()
907 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
DAMDGPUSubtarget.h196 unsigned getWavefrontSize() const { in getWavefrontSize() function
DAMDGPUSubtarget.cpp357 return std::make_pair(1, getWavefrontSize()); in getDefaultFlatWorkGroupSize()
DSILowerI1Copies.cpp107 ST->getWavefrontSize(); in isLaneMaskReg()
DAMDGPUAsmPrinter.cpp1068 alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(), in getSIProgramInfo()
DAMDGPULibCalls.cpp1395 unsigned N = ST.getWavefrontSize(); in fold_wavefrontsize()
DSIRegisterInfo.cpp658 Offset *= ST.getWavefrontSize(); in buildSpillLoadStore()
DSIISelLowering.cpp3707 unsigned Mask = (getSubtarget()->getWavefrontSize() << 1) - 1; in EmitInstrWithCustomInserter()
3720 .addImm(getSubtarget()->getWavefrontSize()); in EmitInstrWithCustomInserter()
4229 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerICMPIntrinsic()
4262 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerFCMPIntrinsic()
5895 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(), in LowerINTRINSIC_WO_CHAIN()
6846 if (WGSize <= ST.getWavefrontSize()) in LowerINTRINSIC_VOID()
10997 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass in getRegClassFor()
DSIInstrInfo.td9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
DAMDGPULegalizerInfo.cpp2458 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize()); in legalizeIntrinsic()
DSIInstrInfo.cpp1245 unsigned WavefrontSize = ST.getWavefrontSize(); in calculateLDSSpillAddress()
5904 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2; in getScratchRsrcWords23()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.cpp252 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { in getWavefrontSize() function
323 return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) / in getWavesPerWorkGroup()
324 getWavefrontSize(STI); in getWavesPerWorkGroup()
DAMDGPUBaseInfo.h76 unsigned getWavefrontSize(const MCSubtargetInfo *STI);