| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterBankInfo.cpp | 47 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
51 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
52 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
55 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
58 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
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| D | X86DomainReassignment.cpp | 45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
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| D | X86InstrInfo.cpp | 2851 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
2852 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
2853 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3070 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
3074 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3078 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3080 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
3083 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3085 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3093 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
258 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
260 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
262 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
264 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
266 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
270 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
283 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
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| D | Mips16InstrInfo.cpp | 116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 775 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
776 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
777 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
778 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
806 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
807 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
809 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
810 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1034 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getStoreOpcodeForSpill()
1035 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getStoreOpcodeForSpill()
[all …]
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| D | PPCVSXCopy.cpp | 54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
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| D | PPCVSXSwapRemoval.cpp | 162 return RC->hasSubClassEq(MRI->getRegClass(Reg)); in isRegInClass()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 124 if (RISCV::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
127 else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
129 else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
151 if (RISCV::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
154 else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
156 else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 437 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
514 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
515 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
528 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
529 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
1078 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && in UpdateOperandRegClass()
2859 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2863 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2867 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2873 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 119 return RC != this && hasSubClassEq(RC); in hasSubClass()
123 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
136 return RC->hasSubClassEq(this); in hasSuperClassEq()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 47 if (!RC.hasSubClassEq(&SubRC)) in verify()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1039 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1050 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1057 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1064 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1075 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1082 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1103 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1119 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1131 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1155 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
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| D | Thumb2InstrInfo.cpp | 148 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
158 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
190 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
199 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
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| D | ThumbRegisterInfo.cpp | 48 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 34 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
38 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
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| D | SystemZInstrInfo.cpp | 553 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
554 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
555 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
580 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
595 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in insertSelect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 897 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
901 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
905 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
909 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
913 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
917 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
921 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
943 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
946 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
949 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
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| D | HexagonConstPropagation.cpp | 2363 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2365 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2367 if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
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| D | HexagonFrameLowering.cpp | 2098 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2100 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.cpp | 283 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineFunction.cpp | 624 RC->hasSubClassEq(VRegRC))) && in addLiveIn()
|