| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 5523 unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1)…
5527 return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5530 return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5535 unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1)…
5537 case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
5544 …gned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5548 return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5553 …ned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5557 return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5562 …ned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
[all …]
|
| /third_party/mesa3d/src/panfrost/bifrost/valhall/test/ |
| D | test-validate-fau.cpp | 49 imm1 = bi_fau((enum bir_fau) (BIR_FAU_IMMEDIATE | 1), false); in ValidateFau()
64 bi_index zero, imm1, imm2, unif, unif_hi, unif2, core_id, lane_id; member in ValidateFau
88 VALID(bi_fma_f32_to(b, bi_register(1), zero, imm1, imm1)); in TEST_F()
90 INVALID(bi_fma_f32_to(b, bi_register(1), zero, imm1, imm2)); in TEST_F()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenFastISel.inc | 9844 …ANE64_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
9848 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1);
9853 …ANE64_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
9856 return fastEmitInst_ri(AArch64::DUPv2i64lane, &AArch64::FPR128RegClass, Op0, Op0IsKill, imm1);
9859 …PLANE64_ri_Predicate_VectorIndexD(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
9861 …urn fastEmit_AArch64ISD_DUPLANE64_MVT_v2i64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1);
9862 …urn fastEmit_AArch64ISD_DUPLANE64_MVT_v2f64_ri_Predicate_VectorIndexD(RetVT, Op0, Op0IsKill, imm1);
9869 …R_ELT_MVT_v2i64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
9873 return fastEmitInst_ri(AArch64::UMOVvi64, &AArch64::GPR64RegClass, Op0, Op0IsKill, imm1);
9878 …R_ELT_MVT_v2f64_ri_Predicate_VectorIndexD(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenFastISel.inc | 3455 …Emit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3459 return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3462 return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3467 …Emit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3469 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
3476 …ned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3480 return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3485 …ed fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3489 return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3494 …gned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
[all …]
|
| /third_party/mesa3d/src/compiler/glsl/ |
| D | lower_blend_equation_advanced.cpp | 36 #define imm1(x) new(mem_ctx) ir_constant((float) (x), 1) macro
229 f->emit(if_tree(less(mincol, imm1(0)), in set_lum()
232 if_tree(greater(maxcol, imm1(1)), in set_lum()
263 f->emit(if_tree(greater(sbase, imm1(0)), in set_lum_sat()
311 f.emit(if_tree(equal(dst_alpha, imm1(0)), in calc_blend_result()
319 f.emit(if_tree(equal(src_alpha, imm1(0)), in calc_blend_result()
405 f.emit(assign(p1, mul(src_alpha, sub(imm1(1), dst_alpha)))); in calc_blend_result()
406 f.emit(assign(p2, mul(dst_alpha, sub(imm1(1), src_alpha)))); in calc_blend_result()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 3322 unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3325 return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3328 unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3331 return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3334 unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3336 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
3337 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
3344 unsigned fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1…
3348 return fastEmitInst_ri(PPC::EXTSWSLI_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3353 unsigned fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1…
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 15231 unsigned fastEmit_ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
15234 return fastEmitInst_ri(X86::ADD8ri, &X86::GR8RegClass, Op0, Op0IsKill, imm1);
15237 unsigned fastEmit_ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
15240 return fastEmitInst_ri(X86::ADD16ri, &X86::GR16RegClass, Op0, Op0IsKill, imm1);
15243 unsigned fastEmit_ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
15246 return fastEmitInst_ri(X86::ADD32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);
15249 unsigned fastEmit_ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
15251 case MVT::i8: return fastEmit_ISD_ADD_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1);
15252 case MVT::i16: return fastEmit_ISD_ADD_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1);
15253 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
[all …]
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 555 ImmediateValue &imm0, ImmediateValue &imm1) in expr() argument
557 struct Storage *const a = &imm0.reg, *const b = &imm1.reg; in expr()
790 ImmediateValue &imm1, in expr() argument
793 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
914 ImmediateValue imm1; in tryCollapseChainedMULs() local
925 if (mul1->src(s1 = 0).getImmediate(imm1) || in tryCollapseChainedMULs()
926 mul1->src(s1 = 1).getImmediate(imm1)) { in tryCollapseChainedMULs()
930 mul1->setSrc(s1, bld.loadImm(NULL, f * imm1.reg.data.f32)); in tryCollapseChainedMULs()
959 if (!insn->src(s2).mod && !insn->src(t2).getImmediate(imm1)) in tryCollapseChainedMULs()
1400 ImmediateValue imm1; in opnd() local
[all …]
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| /third_party/node/deps/v8/src/wasm/ |
| D | wasm-module-builder.cc | 113 void WasmFunctionBuilder::EmitWithU8U8(WasmOpcode opcode, const byte imm1, in EmitWithU8U8() argument
116 body_.write_u8(imm1); in EmitWithU8U8()
|
| D | wasm-module-builder.h | 187 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
|
| /third_party/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 210 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2780 for (unsigned imm1 = 0; imm1 < inputs_imm1_length; imm1++) { in TestOpImmOpImmNEON() local
2789 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2816 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2821 unsigned input_index_imm1 = imm1; in TestOpImmOpImmNEON()
|
| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_32.c | 1662 sljit_uw imm1; in generate_int() local
1705 imm1 = SRC2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8); in generate_int()
1709 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1744 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1764 FAIL_IF(push_inst(compiler, (positive ? MOV : MVN) | RD(reg) | imm1)); in generate_int()
|
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | code-generator-arm64.cc | 2625 uint64_t imm1 = make_uint64(i.InputUint32(1), i.InputUint32(0)); in AssembleArchInstruction() local
2627 __ Movi(i.OutputSimd128Register().V16B(), imm2, imm1); in AssembleArchInstruction()
2746 int64_t imm1 = make_uint64(i.InputInt32(3), i.InputInt32(2)); in AssembleArchInstruction() local
2748 DCHECK_EQ(0, (imm1 | imm2) & (src0 == src1 ? 0xF0F0F0F0F0F0F0F0 in AssembleArchInstruction()
2753 __ Movi(temp, imm2, imm1); in AssembleArchInstruction()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 237 unsigned Op0, bool Op0IsKill, uint64_t imm1, in fastEmitInst_riir() argument
|
| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 2844 uint64_t imm1 = make_uint64(i.InputUint32(1), i.InputUint32(0)); in AssembleArchInstruction() local
2846 __ vmov(dst.low(), base::Double(imm1)); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/wasm/baseline/riscv64/ |
| D | liftoff-assembler-riscv64.h | 1885 uint64_t imm1 = *(reinterpret_cast<const uint64_t*>(shuffle)); in emit_i8x16_shuffle() local
1891 li(kScratchReg, imm1); in emit_i8x16_shuffle()
|
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| D | code-generator-mips64.cc | 2045 uint64_t imm1 = make_uint64(i.InputUint32(1), i.InputUint32(0)); in AssembleArchInstruction() local
2047 __ li(kScratchReg, imm1); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| D | code-generator-riscv64.cc | 2757 int64_t imm1 = make_uint64(i.InputInt32(3), i.InputInt32(2)); in AssembleArchInstruction() local
2763 __ li(kScratchReg, imm1); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | macro-assembler-riscv64.cc | 3978 uint64_t imm1 = *(reinterpret_cast<const uint64_t*>(imms)); in WasmRvvS128const() local
3983 li(kScratchReg, imm1); in WasmRvvS128const()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFormats.td | 3033 ImmOpWithPattern imm1, ImmOpWithPattern imm2>
3034 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4560 // SETPAN #imm1
|
| D | ARMInstrInfo.td | 4659 // SETPAN #imm1
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 1044 def imm1 : NVPTXInst<(outs regclass:$dst),
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 927 // {0} - imm1: #8 or #16
|