| /third_party/mesa3d/src/panfrost/midgard/ |
| D | disassemble.c | 1419 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1441 word->index_reg != 0x7) { in print_load_store_instr()
1445 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1477 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1484 print_ldst_read_reg(fp, word->index_reg); in print_load_store_instr()
1519 if (word->index_reg == 0x7 && ctx->midg_stats.varying_count >= 0) in print_load_store_instr()
1525 if (word->index_reg == 0x7 && ctx->midg_stats.attribute_count >= 0) in print_load_store_instr()
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| D | midgard_compile.c | 1239 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_ubo_read()
1451 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_varying_read()
1538 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_image_op()
1553 ins.load_store.index_reg = REGISTER_LDST_ZERO; in emit_attr_read()
1710 ld.load_store.index_reg = REGISTER_LDST_ZERO; in emit_special()
1900 ld.load_store.index_reg = target >> 2; in emit_intrinsic()
1916 ld.load_store.index_reg = REGISTER_LDST_ZERO; in emit_intrinsic()
1936 ld.load_store.index_reg = index >> 2; in emit_intrinsic()
1947 ld.load_store.index_reg = REGISTER_LDST_ZERO; in emit_intrinsic()
2031 st.load_store.index_reg = REGISTER_LDST_ZERO; in emit_intrinsic()
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| D | midgard_address.c | 277 ins->load_store.index_reg = REGISTER_LDST_ZERO; in mir_set_offset()
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| D | midgard_emit.c | 617 ldst.index_reg = SSA_REG_FROM_FIXED(ins->src[2]) - REGISTER_LDST_BASE; in load_store_from_instr()
619 ldst.index_comp = midgard_ldst_comp(ldst.index_reg, ins->swizzle[2][0], sz); in load_store_from_instr()
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| D | midgard.h | 768 unsigned index_reg : 3; member
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| D | compiler.h | 585 .index_reg = REGISTER_LDST_ZERO, in v_load_store_scratch()
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| D | midgard_ra.c | 1122 .index_reg = REGISTER_LDST_ZERO, in mir_demote_uniforms()
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_assembler.cpp | 611 output.index_gpr = instr.index_reg(); in visit()
985 m_bc->index_reg[idx] != (unsigned)addr.sel() in emit_index_reg()
1033 m_bc->index_reg[idx] = addr.sel(); in emit_index_reg()
1123 if (m_bc->index_reg[1] == dst.sel && in copy_dst()
1127 if (m_bc->index_reg[0] == dst.sel && in copy_dst()
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| D | sfn_instr_export.h | 176 unsigned index_reg() const {assert(m_export_index->sel() >= 0); return m_export_index->sel();} in index_reg() function
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 3671 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmul() local
3672 fmul<float>(vform, dst, src1, index_reg); in fmul()
3675 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); in fmul() local
3676 fmul<double>(vform, dst, src1, index_reg); in fmul()
3687 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmla() local
3688 fmla<float>(vform, dst, src1, index_reg); in fmla()
3691 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); in fmla() local
3692 fmla<double>(vform, dst, src1, index_reg); in fmla()
3703 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmls() local
3704 fmls<float>(vform, dst, src1, index_reg); in fmls()
[all …]
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_asm.h | 281 unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */ member
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| D | eg_asm.c | 191 alu.src[0].sel = bc->index_reg[id]; in egcm_load_index_reg()
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| D | r600_shader.c | 941 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg; in get_address_file_reg()
3651 ctx.bc->index_reg[0] = ++regno; in r600_shader_from_tgsi()
3652 ctx.bc->index_reg[1] = ++regno; in r600_shader_from_tgsi()
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| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 5689 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index); in fmul() local
5690 fmul<SimFloat16>(vform, dst, src1, index_reg); in fmul()
5692 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmul() local
5693 fmul<float>(vform, dst, src1, index_reg); in fmul()
5696 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); in fmul() local
5697 fmul<double>(vform, dst, src1, index_reg); in fmul()
5711 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index); in fmla() local
5712 fmla<SimFloat16>(vform, dst, dst, src1, index_reg); in fmla()
5714 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmla() local
5715 fmla<float>(vform, dst, dst, src1, index_reg); in fmla()
[all …]
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| /third_party/node/deps/v8/src/wasm/baseline/ |
| D | liftoff-compiler.cc | 4634 Register index_reg = in AtomicWait() local
4637 if (index_reg == no_reg) return; in AtomicWait()
4638 LiftoffRegList pinned = {index_reg}; in AtomicWait()
4639 AlignmentCheckMem(decoder, value_kind_size(kind), imm.offset, index_reg, in AtomicWait()
4644 __ cache_state()->is_used(LiftoffRegister(index_reg)) in AtomicWait()
4646 : index_reg; in AtomicWait()
4648 __ emit_ptrsize_zeroextend_i32(index_plus_offset, index_reg); in AtomicWait()
4682 Register index_reg = BoundsCheckMem(decoder, kInt32Size, imm.offset, in AtomicNotify() local
4684 if (index_reg == no_reg) return; in AtomicNotify()
4685 LiftoffRegList pinned = {index_reg}; in AtomicNotify()
[all …]
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| /third_party/pcre2/pcre2/src/ |
| D | pcre2_jit_simd_inc.h | 1142 sljit_s32 base_reg, sljit_s32 index_reg) in load_from_mem_vector() argument
1146 instruction[0] = (sljit_u16)(0xe700 | (dst_vreg << 4) | index_reg); in load_from_mem_vector()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_generator.cpp | 814 struct brw_reg index_reg = brw_vec1_grf( in generate_tcs_input_urb_offsets() local
818 retype(index_reg, BRW_REGISTER_TYPE_UD)); in generate_tcs_input_urb_offsets()
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| /third_party/node/deps/v8/src/execution/s390/ |
| D | simulator-s390.cc | 2982 #define GET_ADDRESS(index_reg, base_reg, offset) \ argument
2983 (((index_reg) == 0) ? 0 : get_register(index_reg)) + \
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