| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 219 let isAllocatable = 0;
224 let isAllocatable = 0;
261 let isAllocatable = 0;
415 let isAllocatable = 0;
421 let isAllocatable = 0;
427 let isAllocatable = 0;
459 let isAllocatable = 0;
477 let isAllocatable = 0;
495 let isAllocatable = 0;
501 let isAllocatable = 0;
[all …]
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| D | R600RegisterInfo.td | 160 let isAllocatable = 0 in {
206 } // End isAllocatable = 0
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| D | GCNNSAReassign.cpp | 133 if (!MRI->isAllocatable(Reg)) in canAssign()
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| D | SIMachineFunctionInfo.cpp | 371 return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) && in allocateVGPRSpillToAGPR()
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| D | SIFrameLowering.cpp | 307 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) { in getReservedPrivateSegmentBufferReg()
370 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) { in getReservedPrivateSegmentWaveByteOffsetReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 174 if (!RC || RC->isAllocatable()) in getAllocatableClass()
180 if (SubRC->isAllocatable()) in getAllocatableClass()
211 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
227 if (C->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
530 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
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| D | RegAllocFast.cpp | 674 if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) && in allocVirtReg()
695 if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && in allocVirtReg()
1062 if (!MRI->isAllocatable(Reg)) continue; in allocateInstruction()
1172 if (!Reg || !Reg.isPhysical() || !MRI->isAllocatable(Reg)) in allocateInstruction()
1257 if (MRI->isAllocatable(LI.PhysReg)) in allocateBasicBlock()
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| D | CalcSpillWeights.cpp | 255 if (Register::isVirtualRegister(hint) || mri.isAllocatable(hint)) in weightCalcHelper()
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| D | AggressiveAntiDepBreaker.cpp | 650 if (!MRI.isAllocatable(NewSuperReg)) continue; in FindSuitableFreeRegisters()
861 if (!MRI.isAllocatable(AntiDepReg)) { in BreakAntiDependencies()
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| D | CriticalAntiDepBreaker.cpp | 572 if (!MRI.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
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| D | RegisterPressure.cpp | 524 } else if (MRI.isAllocatable(Reg)) { in pushReg()
559 } else if (MRI.isAllocatable(Reg)) { in pushRegLanes()
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| D | MachineCSE.cpp | 345 if (MRI->isAllocatable(PhysDefs[i].second) || in PhysRegDefsReach()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 361 let Size = 32, isAllocatable = 0 in
368 let isAllocatable = 0 in
371 let Size = 64, isAllocatable = 0 in
376 let Size = 32, isAllocatable = 0 in
386 let Size = 64, isAllocatable = 0 in
397 let isAllocatable = 0 in
403 let Size = 32, isAllocatable = 0 in
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| D | HexagonBlockRanges.cpp | 225 if (RC->isAllocatable()) in HexagonBlockRanges()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 57 let isAllocatable = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 398 let isAllocatable = 0 in
407 let isAllocatable = 0 in
541 let isAllocatable = 0;
548 let isAllocatable = 0;
565 let isAllocatable = 0;
569 let isAllocatable = 0;
573 let isAllocatable = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 62 let isAllocatable = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 41 let isAllocatable = allocatable in
295 let isAllocatable = 0, CopyCost = -1 in
302 let isAllocatable = 0 in
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 114 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
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| D | MachineRegisterInfo.h | 915 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 375 let isAllocatable = 0;
378 let isAllocatable = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 263 let isAllocatable = 0;
354 let isAllocatable = 0;
420 let isAllocatable = 0;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 88 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 88 bool isAllocatable() const { return Allocatable; } in isAllocatable() function
|