| /third_party/typescript/tests/cases/conformance/salsa/ |
| D | typeFromJSInitializer.ts | 62 const isUndef = v => v === undefined; constant
66 const g = e.filter(isUndef);
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| /third_party/typescript/tests/baselines/reference/ |
| D | typeFromJSInitializer.types | 243 const isUndef = v => v === undefined;
244 >isUndef : (v: unknown) => v is undefined
258 const g = e.filter(isUndef);
260 >e.filter(isUndef) : undefined[]
264 >isUndef : (v: unknown) => v is undefined
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| D | typeFromJSInitializer.symbols | 179 const isUndef = v => v === undefined;
180 >isUndef : Symbol(isUndef, Decl(a.js, 55, 5))
190 const g = e.filter(isUndef);
195 >isUndef : Symbol(isUndef, Decl(a.js, 55, 5))
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| D | typeFromJSInitializer.errors.txt | 89 const isUndef = v => v === undefined;
93 const g = e.filter(isUndef);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 143 if (MO.isUndef()) in determineKillsAndDefs()
212 if (MO.isUndef()) in forward()
331 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) in findSurvivorReg()
545 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
729 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
744 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
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| D | MachineInstrBundle.cpp | 170 if (MO.isUndef()) in finalizeBundle()
224 bool isUndef = UndefUseSet.count(Reg); in finalizeBundle() local
225 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
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| D | ExpandPostRAPseudos.cpp | 148 if (IdentityCopy || SrcMO.isUndef()) { in LowerCopy()
153 if (SrcMO.isUndef() || MI->getNumOperands() > 2) { in LowerCopy()
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| D | BreakFalseDeps.cpp | 110 assert(MO.isUndef() && "Expected undef machine operand"); in pickBestRegisterForUndef()
131 if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() || in pickBestRegisterForUndef()
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| D | LiveDebugVariables.cpp | 116 bool isUndef() const { return locNo() == UndefLocNo; } in isUndef() function in DbgValueLocation
279 if (!Loc.isUndef() && Loc.locNo() > LocNo) in removeLocationIfUnused()
544 if (I.value().isUndef()) in print()
857 if (!I.value().isUndef()) in computeIntervals()
1248 if (Loc.isUndef()) in rewriteLocations()
1315 MachineOperand MO = !Loc.isUndef() ? in insertDebugValue()
1375 !Loc.isUndef() ? SpillOffsets.find(Loc.locNo()) : SpillOffsets.end(); in emitDebugValues()
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| D | RegAllocFast.cpp | 456 if (MO.isUndef()) in usePhysReg()
753 assert(MO.isUndef() && "expected undef use"); in allocVirtRegUndef()
879 if (MO.isDef() && MO.isUndef()) in setPhysReg()
1102 if (MO.isUndef()) { in allocateInstruction()
1131 assert(MO.isUndef() && "Should only have undef virtreg uses left"); in allocateInstruction()
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| D | TargetInstrInfo.cpp | 182 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef(); in commuteInstructionImpl()
183 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef(); in commuteInstructionImpl()
1228 if (MOReg.isUndef()) in getRegSequenceInputs()
1253 if (MOReg.isUndef()) in getExtractSubregInputs()
1279 if (MOInsertedReg.isUndef()) in getInsertSubregInputs()
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| D | DeadMachineInstructionElim.cpp | 90 assert(U.isUndef() && "'Undef' use on a 'dead' register is found!"); in isDead()
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| D | UnreachableBlockElim.cpp | 188 !Input.isUndef()) { in runOnMachineFunction()
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| D | VirtRegMap.cpp | 352 if (MO.isUndef()) in readsUndefSubreg()
386 if (MI.getOperand(1).isUndef() || MI.getNumOperands() > 2) { in handleIdentityCopy()
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| D | PHIElimination.cpp | 234 if (!isImplicitlyDefined(MO.getReg(), MRI) && !MO.isUndef()) in allPhiOperandsUndefined()
378 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() || in LowerPHINode()
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| D | RegisterPressure.cpp | 504 if (!MO.isUndef() && !MO.isInternalRead()) in collectOperand()
536 if (!MO.isUndef() && !MO.isInternalRead()) in collectOperandLanes()
541 if (MO.isUndef()) in collectOperandLanes()
1228 if (MO.isUndef()) in findUseBetween()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 393 bool isUndef() const { in isUndef() function
458 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
755 bool isUndef = false, bool isDebug = false);
781 bool isUndef = false,
793 Op.IsUndef = isUndef;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 166 while (i != e && N->getOperand(i).isUndef()) in isBuildVectorAllOnes()
195 if (N->getOperand(i) != NotZero && !N->getOperand(i).isUndef()) in isBuildVectorAllOnes()
209 if (Op.isUndef()) in isBuildVectorAllZeros()
242 if (Op.isUndef()) in isBuildVectorOfConstantSDNodes()
255 if (Op.isUndef()) in isBuildVectorOfConstantFPSDNodes()
269 return all_of(N->op_values(), [](SDValue Op) { return Op.isUndef(); }); in allOperandsUndef()
285 if (AllowUndefs && Op.getOperand(i).isUndef()) { in matchUnaryPredicate()
319 bool LHSUndef = AllowUndefs && LHSOp.isUndef(); in matchBinaryPredicate()
320 bool RHSUndef = AllowUndefs && RHSOp.isUndef(); in matchBinaryPredicate()
1615 if (N1.isUndef() && N2.isUndef()) in getVectorShuffle()
[all …]
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| D | DAGCombiner.cpp | 870 if (Op.isUndef()) in isConstantOrConstantVector()
1985 if (!CanFoldNonConst && !NewCT.isUndef() && in foldBinOpIntoSelect()
1992 if (!CanFoldNonConst && !NewCF.isUndef() && in foldBinOpIntoSelect()
2101 if (N0.isUndef()) in visitADDLike()
2104 if (N1.isUndef()) in visitADDLike()
2342 if (N0.isUndef() || N1.isUndef()) in visitADDSAT()
3140 if (N0.isUndef()) in visitSUB()
3142 if (N1.isUndef()) in visitSUB()
3290 if (N0.isUndef() || N1.isUndef()) in visitSUBSAT()
3414 if (N0.isUndef() || N1.isUndef()) in visitMULFIX()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 229 bool AddRegUndef = AddendMI->getOperand(1).isUndef(); in processBlock()
230 bool KilledProdRegUndef = MI.getOperand(KilledProdOp).isUndef(); in processBlock()
231 bool OtherProdRegUndef = MI.getOperand(OtherProdOp).isUndef(); in processBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 301 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in canAddPseudoFlagDep()
310 if (!MO.isReg() || MO.isUndef() || MO.isDef()) in canAddPseudoFlagDep()
975 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in UpdateCPSRDef()
990 if (!MO.isReg() || MO.isUndef() || MO.isDef()) in UpdateCPSRUse()
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| D | ARMLoadStoreOptimizer.cpp | 1014 unsigned PRegNum = PMO.isUndef() ? std::numeric_limits<unsigned>::max() in FormCandidates()
1067 unsigned RegNum = MO.isUndef() ? std::numeric_limits<unsigned>::max() in FormCandidates()
1617 if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef()) in isMemoryOp()
1621 if (MI.getOperand(1).isUndef()) in isMemoryOp()
1686 bool EvenUndef = MI->getOperand(0).isUndef(); in FixInvalidRegPairOp()
1689 bool OddUndef = MI->getOperand(1).isUndef(); in FixInvalidRegPairOp()
1691 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyMemIntrinsicResults.cpp | 125 if (!O.isUndef()) { in replaceDominatedUses()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 321 if (!Op.isReg() || !Op.isUse() || Op.isUndef()) in computeInitialLiveRanges()
337 if (!Op.isReg() || !Op.isDef() || Op.isUndef()) in computeInitialLiveRanges()
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| D | HexagonISelLoweringHVX.cpp | 379 if (isUndef(Words[i])) in buildHvxVectorReg()
422 if (isUndef(V)) { in buildHvxVectorReg()
553 SDValue W0 = isUndef(PredV) in createHvxPrefixPred()
623 SDValue Ext = !V.isUndef() ? DAG.getZExtOrTrunc(V, dl, MVT::i8) in buildHvxVectorPred()
636 if (!Values[I+B].isUndef()) in buildHvxVectorPred()
649 assert(Values[I+B].isUndef() || Values[I+B] == F); in buildHvxVectorPred()
1086 else if (V.isUndef()) in LowerHvxConcatVectors()
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