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Searched refs:kFormat4S (Results 1 – 13 of 13) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm64/
Dregister-arm64.cc13 DCHECK(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D || in VectorFormatHalfWidth()
18 case kFormat4S: in VectorFormatHalfWidth()
40 return kFormat4S; in VectorFormatDoubleWidth()
66 case kFormat4S: in VectorFormatFillQ()
67 return kFormat4S; in VectorFormatFillQ()
85 case kFormat4S: in VectorFormatHalfWidthDoubleLanes()
90 return kFormat4S; in VectorFormatHalfWidthDoubleLanes()
104 return kFormat4S; in VectorFormatDoubleLanes()
111 DCHECK(vform == kFormat16B || vform == kFormat8H || vform == kFormat4S); in VectorFormatHalfLanes()
117 case kFormat4S: in VectorFormatHalfLanes()
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Dinstructions-arm64.cc391 kFormat2S, kFormat4S, kFormat1D, kFormat2D, kFormatB, in GetVectorFormat()
Dregister-arm64.h281 kFormat4S = NEON_4S, enumerator
/third_party/vixl/src/aarch64/
Dinstructions-aarch64.cc1009 case kFormat4S: in VectorFormatHalfWidth()
1037 return kFormat4S; in VectorFormatDoubleWidth()
1071 case kFormat4S: in VectorFormatFillQ()
1072 return kFormat4S; in VectorFormatFillQ()
1091 case kFormat4S: in VectorFormatHalfWidthDoubleLanes()
1096 return kFormat4S; in VectorFormatHalfWidthDoubleLanes()
1117 return kFormat4S; in VectorFormatDoubleLanes()
1126 VIXL_ASSERT(vform == kFormat16B || vform == kFormat8H || vform == kFormat4S); in VectorFormatHalfLanes()
1132 case kFormat4S: in VectorFormatHalfLanes()
1246 case kFormat4S: in RegisterSizeInBitsFromFormat()
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Dinstructions-aarch64.h186 kFormat4S = NEON_4S, enumerator
855 kFormat4S, in GetVectorFormat()
Dsimulator-aarch64.cc1107 case kFormat4S: in Simulator()
1147 case kFormat4S: in Simulator()
7748 VectorFormat vform = instr->GetNEONQ() ? kFormat4S : kFormat2S; in Simulator()
7790 } else if ((vform == kFormat2S) || (vform == kFormat4S)) { in Simulator()
7831 vform = kFormat4S; in Simulator()
7843 VectorFormat vform = instr->GetNEONQ() ? kFormat4S : kFormat2S; in Simulator()
8226 vf = ((instr->GetNEONLSSize() & 1) == 0) ? kFormat4S : kFormat2D; in Simulator()
8394 vform = (q == 1) ? kFormat4S : kFormat2S; in Simulator()
8403 vform = (q == 1) ? kFormat4S : kFormat2S; in Simulator()
8427 vform = q ? kFormat4S : kFormat2S; in Simulator()
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Dlogic-aarch64.cc2192 (dstform == kFormat4S)) { in extractnarrow()
5692 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmul()
5714 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmla()
5736 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmls()
5758 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmulx()
7750 VIXL_ASSERT((vform_dst == kFormat4S) || (vform_dst == kFormatVnS)); in matmul()
Ddisasm-aarch64.cc2867 if ((vform_dst != kFormat2S) && (vform_dst != kFormat4S)) { in Disassembler()
/third_party/node/deps/v8/src/wasm/baseline/arm64/
Dliftoff-assembler-arm64.h2015 tmp = temps.AcquireV(kFormat4S); in emit_f32x4_pmin()
2032 tmp = temps.AcquireV(kFormat4S); in emit_f32x4_pmax()
2222 liftoff::EmitAllTrue(this, dst, src, kFormat4S); in emit_i32x4_alltrue()
2243 this, dst.fp().V4S(), lhs.fp().V4S(), rhs.gp(), kFormat4S); in emit_i32x4_shl()
2256 this, dst.fp().V4S(), lhs.fp().V4S(), rhs.gp(), kFormat4S); in emit_i32x4_shr_s()
2261 liftoff::EmitSimdShiftRightImmediate<kFormat4S, liftoff::ShiftSign::kSigned>( in emit_i32x4_shri_s()
2270 this, dst.fp().V4S(), lhs.fp().V4S(), rhs.gp(), kFormat4S); in emit_i32x4_shr_u()
2275 liftoff::EmitSimdShiftRightImmediate<kFormat4S, in emit_i32x4_shri_u()
2323 VRegister tmp1 = scope.AcquireV(kFormat4S); in emit_i32x4_dot_i16x8_s()
2324 VRegister tmp2 = scope.AcquireV(kFormat4S); in emit_i32x4_dot_i16x8_s()
/third_party/node/deps/v8/src/compiler/backend/arm64/
Dcode-generator-arm64.cc1077 kFormat4S); in AssembleArchInstruction()
1085 kFormat4S); in AssembleArchInstruction()
1097 kFormat4S); in AssembleArchInstruction()
1105 kFormat4S); in AssembleArchInstruction()
2485 VRegister tmp1 = scope.AcquireV(kFormat4S); in AssembleArchInstruction()
2486 VRegister tmp2 = scope.AcquireV(kFormat4S); in AssembleArchInstruction()
2517 VRegister temp = scope.AcquireV(kFormat4S); in AssembleArchInstruction()
2538 VRegister temp = scope.AcquireV(kFormat4S); in AssembleArchInstruction()
2686 VRegister temp = scope.AcquireV(kFormat4S); in AssembleArchInstruction()
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc1729 srcform = kFormat4S; in ExtractNarrow()
1733 srcform = kFormat4S; in ExtractNarrow()
1739 case kFormat4S: in ExtractNarrow()
3635 DCHECK_EQ(vform, kFormat4S); in NEON_FPPAIRWISE_LIST()
3671 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmul()
3687 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmla()
3703 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmls()
3719 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); in fmulx()
Dsimulator-arm64.cc1257 case kFormat4S: in GetPrintRegisterFormat()
1282 case kFormat4S: in GetPrintRegisterFormatFP()
5077 vf = ((instr->NEONLSSize() & 1) == 0) ? kFormat4S : kFormat2D; in NEONLoadStoreSingleStructHelper()
5245 vform = (q == 1) ? kFormat4S : kFormat2S; in VisitNEONModifiedImmediate()
5254 vform = (q == 1) ? kFormat4S : kFormat2S; in VisitNEONModifiedImmediate()
5275 vform = q ? kFormat4S : kFormat2S; in VisitNEONModifiedImmediate()
/third_party/vixl/test/aarch64/
Dtest-api-aarch64.cc282 VIXL_CHECK(VRegister(10, kFormat4S).Is(v10.V4S())); in TEST()