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Searched refs:kFormatVnB (Results 1 – 7 of 7) sorted by relevance

/third_party/vixl/src/aarch64/
Dinstructions-aarch64.cc569 case kFormatVnB: in GetSVEMulZmAndIndex()
1020 return kFormatVnB; in VectorFormatHalfWidth()
1046 case kFormatVnB: in VectorFormatDoubleWidth()
1098 return kFormatVnB; in VectorFormatHalfWidthDoubleLanes()
1160 case kFormatVnB: in IsSVEFormat()
1176 return kFormatVnB; in SVEFormatFromLaneSizeInBytes()
1267 case kFormatVnB: in LaneSizeInBitsFromFormat()
1307 case kFormatVnB: in LaneSizeInBytesLog2FromFormat()
Dsimulator-aarch64.cc727 dup_immediate(kFormatVnB, ones, 0xff); in Simulator()
728 mov_zeroing(kFormatVnB, result, pg, ones); in Simulator()
736 dup_immediate(kFormatVnB, zero, 0); in Simulator()
1125 case kFormatVnB: in Simulator()
2067 ext(kFormatVnB, zd, zn, zn2, index); in Simulator()
2077 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Simulator()
2078 histogram(kFormatVnB, in Simulator()
2089 pmul(kFormatVnB, zd, zn, zm); in Simulator()
2104 if (vform == kFormatVnB) vform = kFormatVnH; in Simulator()
2123 if (vform == kFormatVnB) vform = kFormatVnH; in Simulator()
[all …]
Ddisasm-aarch64.cc5242 if (instr->GetSVEVectorFormat() != kFormatVnB) { in Disassembler()
5312 if ((instr->GetSVEVectorFormat() == kFormatVnB) && in Disassembler()
5771 if (instr->GetSVEVectorFormat() != kFormatVnB) { in Disassembler()
5921 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
5965 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
6140 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
7689 if (instr->GetSVEVectorFormat() != kFormatVnB) { in Disassembler()
7706 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
7739 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
7775 if (instr->GetSVEVectorFormat() == kFormatVnB) { in Disassembler()
[all …]
Dlogic-aarch64.cc2511 return ext(kFormatVnB, dst, src, src, index); in rotate_elements_right()
6041 mov(kFormatVnB, tmp, src); in fcvtxn()
6396 int first_pg = GetFirstActive(kFormatVnB, pg); in pfirst()
6397 VIXL_ASSERT(first_pg < LaneCountFromFormat(kFormatVnB)); in pfirst()
6399 if (first_pg >= 0) dst.SetActive(kFormatVnB, first_pg, true); in pfirst()
6588 dup_immediate(kFormatVnB, zero, 0); in FTMaddHelper()
7345 for (int i = 0; i < LaneCountFromFormat(kFormatVnB); i++) { in brka()
7346 if (pg.IsActive(kFormatVnB, i)) { in brka()
7347 pd.SetActive(kFormatVnB, i, !break_); in brka()
7348 break_ |= pn.IsActive(kFormatVnB, i); in brka()
[all …]
Dinstructions-aarch64.h209 kFormatVnB = SVE_B | kFormatSVE, enumerator
325 return kFormatVnB;
/third_party/vixl/test/aarch64/
Dtest-api-aarch64.cc296 VIXL_CHECK(ZRegister(0, kFormatVnB).Is(z0.VnB())); in TEST()
311 VIXL_CHECK(PRegisterWithLaneSize(0, kFormatVnB).Is(p0.VnB())); in TEST()
1566 temps.Include(ZRegister(17, kFormatVnB)); in TEST()
1598 temps.Exclude(ZRegister(17, kFormatVnB)); in TEST()
1651 temps.Include(PRegisterWithLaneSize(12, kFormatVnB)); in TEST()
1683 temps.Exclude(PRegisterWithLaneSize(12, kFormatVnB)); in TEST()
Dtest-trace-aarch64.cc3023 reg.SetActive(kFormatVnB, bit, ((bit + 1) % (r + 2)) != 0); in TraceTestHelper()