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Searched refs:kSRegSize (Results 1 – 25 of 25) sorted by relevance

/third_party/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc479 TEST_SVE(sve_mla_mls_s) { MlaMlsHelper(config, kSRegSize); } in TEST_SVE()
1670 ASSERT_EQUAL_64(-core.GetSVELaneCount(kSRegSize), x23); in TEST_SVE()
1779 ASSERT_EQUAL_64(0x40000000 - core.GetSVELaneCount(kSRegSize), x22); in TEST_SVE()
1912 int s_lane_count = core.GetSVELaneCount(kSRegSize); in TEST_SVE()
2060 int s_lane_count = core.GetSVELaneCount(kSRegSize); in TEST_SVE()
2220 int s_lane_count = core.GetSVELaneCount(kSRegSize); in TEST_SVE()
2279 int s_lane_count = core.GetSVELaneCount(kSRegSize); in TEST_SVE()
2284 uint64_t s_mask = GetUintMask(kSRegSize); in TEST_SVE()
3206 PnextHelper(config, kSRegSize, in0, in0, exp00); in TEST_SVE()
3207 PnextHelper(config, kSRegSize, in1, in0, exp10); in TEST_SVE()
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Dtest-utils-aarch64.cc537 s[i] = VRegister(n, kSRegSize); in PopulateVRegisterArray()
739 case kSRegSize: in GetSignallingNan()
806 case kSRegSize: in SetFpData()
877 SetFpData(masm, kSRegSize, kInputFloatBasic, lcg_mult); in InitialiseRegisterFp()
Dtest-simulator-aarch64.cc242 VIXL_ASSERT((d_size == kDRegSize) || (d_size == kSRegSize) || in Test1Op_Helper()
244 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize) || in Test1Op_Helper()
268 } else if (n_size == kSRegSize) { in Test1Op_Helper()
278 } else if (d_size == kSRegSize) { in Test1Op_Helper()
387 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize) || in Test2Op_Helper()
403 bool float_op = reg_size == kSRegSize; in Test2Op_Helper()
544 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize) || in Test3Op_Helper()
561 bool single_op = reg_size == kSRegSize; in Test3Op_Helper()
702 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmp_Helper()
843 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmpZero_Helper()
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Dtest-api-aarch64.cc248 VIXL_CHECK(VRegister(2, kSRegSize).Is(s2)); in TEST()
255 VIXL_CHECK(VRegister(2, kSRegSize, 1).Is(s2)); in TEST()
259 VIXL_CHECK(VRegister(0, kSRegSize, 2).Is(v0.V2H())); in TEST()
292 VIXL_CHECK(ZRegister(2, kSRegSize).Is(z2.VnS())); in TEST()
307 VIXL_CHECK(PRegisterWithLaneSize(2, kSRegSize).Is(p2.VnS())); in TEST()
328 VIXL_CHECK(CPURegister(4, kSRegSize, CPURegister::kVRegister).Is(s4)); in TEST()
581 VIXL_CHECK(p14.VnS().GetLaneSizeInBits() == kSRegSize); in TEST()
1174 VRegister temp = temps.AcquireVRegisterOfSize(kSRegSize); in TEST()
Dtest-utils-aarch64.h179 case kSRegSize: in zreg_lane()
Dtest-assembler-aarch64.cc7832 ASSERT_EQUAL_FP64(RawbitsToDouble((base_d >> kSRegSize) | in TEST()
7833 ((2 * base_d) << kSRegSize)), in TEST()
7837 ASSERT_EQUAL_FP32(RawbitsToFloat((4 * base_d) >> kSRegSize), s17); in TEST()
7932 VIXL_CHECK(array[12] == ((1 * low_base) << kSRegSize)); in TEST()
7933 VIXL_CHECK(array[13] == (((2 * low_base) << kSRegSize) | (1 * high_base))); in TEST()
7934 VIXL_CHECK(array[14] == (((3 * low_base) << kSRegSize) | (2 * high_base))); in TEST()
7935 VIXL_CHECK(array[15] == (((4 * low_base) << kSRegSize) | (3 * high_base))); in TEST()
7936 VIXL_CHECK(array[16] == (((1 * low_base) << kSRegSize) | (4 * high_base))); in TEST()
7937 VIXL_CHECK(array[17] == (((2 * low_base) << kSRegSize) | (1 * high_base))); in TEST()
7938 VIXL_CHECK(array[18] == (((3 * low_base) << kSRegSize) | (2 * high_base))); in TEST()
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/third_party/vixl/src/aarch64/
Dlogic-aarch64.cc887 VIXL_ASSERT(static_cast<unsigned>(lane_size_in_bits) <= kSRegSize); in PolynomialMult()
2149 VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) <= kSRegSize); in saddv()
2420 VIXL_ASSERT(LaneSizeInBitsFromFormat(vformsrc) <= kSRegSize); in addlp()
2541 case kSRegSize: in fadda()
2597 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcadd()
2676 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmla()
2693 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmla()
5006 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { \
5050 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in frecps()
5082 } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in frsqrts()
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Dregisters-aarch64.h448 VIXL_STATIC_ASSERT(kSRegSize == kWRegSize);
478 case kSRegSize: in EncodeSizeInBits()
652 ZRegister VnS() const { return ZRegister(GetCode(), kSRegSize); } in VnS()
785 return PRegisterWithLaneSize(GetCode(), kSRegSize); in VnS()
810 V(SRegister, kSRegSize, VRegister) \
Dinstructions-aarch64.h67 const unsigned kSRegSize = 32; variable
69 const unsigned kSRegSizeInBytes = kSRegSize / 8;
Dinstructions-aarch64.cc39 (reg_size == kSRegSize) || (reg_size == kDRegSize)); in RepeatBitsAcrossReg()
1237 return kSRegSize; in RegisterSizeInBitsFromFormat()
Dmacro-assembler-sve-aarch64.cc394 case kSRegSize: in Cpy()
830 case kSRegSize: in Fdup()
851 case kSRegSize: in Fdup()
877 case kSRegSize: in Fdup()
Dassembler-sve-aarch64.cc57 VIXL_ASSERT((lane_size == kSRegSize) || (lane_size == kDRegSize)); in adr()
76 op = (lane_size == kSRegSize) ? ADR_z_az_s_same_scaled in adr()
4512 case kSRegSize: in SVEGatherPrefetchVectorPlusImmediateHelper()
4546 case kSRegSize: in SVEGatherPrefetchScalarPlusImmediateHelper()
4579 case kSRegSize: in SVEContiguousPrefetchScalarPlusScalarHelper()
4617 case kSRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4642 case kSRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4667 case kSRegSize: in SVEContiguousPrefetchScalarPlusVectorHelper()
4743 SVEPrefetchHelper(prfop, pg, addr, kSRegSize); in prfw()
5335 case kSRegSize: in sdot()
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Dsimulator-aarch64.cc909 (reg_size == kSRegSize) || (reg_size == kDRegSize)); in Simulator()
1402 case kSRegSize: in Simulator()
9387 sxt(vform, temp, temp, kSRegSize); in Simulator()
9390 uxt(vform, temp, temp, kSRegSize); in Simulator()
10439 dst_data_size = kSRegSize; in Simulator()
10454 dst_data_size = kSRegSize; in Simulator()
10464 dst_data_size = kSRegSize; in Simulator()
10465 src_data_size = kSRegSize; in Simulator()
10470 src_data_size = kSRegSize; in Simulator()
10608 src_data_size = kSRegSize; in Simulator()
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Ddisasm-aarch64.cc2933 if ((ls_dst == kDRegSize) || (ls_dst == kSRegSize)) { in Disassembler()
2942 VIXL_ASSERT((ls_dst == kSRegSize) || (ls_dst == kDRegSize)); in Disassembler()
9237 case kSRegSize: in Disassembler()
9587 reg_size = kSRegSize; in Disassembler()
Dmacro-assembler-aarch64.h1004 PushSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PushSRegList()
1007 PopSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PopSRegList()
1074 PeekSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PeekSRegList()
1077 PokeSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PokeSRegList()
Dassembler-aarch64.cc5983 (width == kSRegSize) || (width == kDRegSize)); in IsImmLogical()
6190 case kSRegSize: in LoadOpFor()
6213 case kSRegSize: in StoreOpFor()
Dsimulator-aarch64.h1597 case kSRegSize:
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc3266 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { \
3302 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frecps()
3387 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in frsqrts()
3435 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp()
3447 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fcmp_zero()
3464 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabscmp()
3495 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmla()
3522 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fmls()
3545 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fneg()
3570 if (LaneSizeInBytesFromFormat(vform) == kSRegSize) { in fabs_()
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Dsimulator-arm64.h1005 (sizeof(T) == kSRegSize) || (sizeof(T) == kDRegSize) || in vreg()
1044 case kSRegSize: in vreg()
1067 (sizeof(value) == kSRegSize) || (sizeof(value) == kDRegSize) ||
1119 (sizeof(value) == kSRegSize) || in set_vreg_no_log()
1284 static_assert(sizeof(value) == kSRegSize, in GetPrintRegisterFormat()
1305 case kSRegSize: in GetPrintRegisterFormatForSizeFP()
1311 if ((GetPrintRegLaneSizeInBytes(format) == kSRegSize) || in GetPrintRegisterFormatTryFP()
Dsimulator-arm64.cc1222 case kSRegSize: in GetPrintRegisterFormatForSize()
1235 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size."); in GetPrintRegisterFormatForSize()
1453 DCHECK((lane_size_in_bytes == kSRegSize) || in PrintVRegisterFPHelper()
1466 const char* name = (lane_size_in_bytes == kSRegSize) in PrintVRegisterFPHelper()
1482 double value = (lane_size_in_bytes == kSRegSize) in PrintVRegisterFPHelper()
2205 DCHECK_EQ(access_size, static_cast<unsigned>(kSRegSize)); in LoadStorePairHelper()
2241 DCHECK_EQ(access_size, static_cast<unsigned>(kSRegSize)); in LoadStorePairHelper()
/third_party/vixl/examples/aarch64/
Dneon-matrix-multiply.cc52 VRegister v_in = VRegister(in_column, kSRegSize); in GenerateMultiplyColumn()
/third_party/vixl/benchmarks/aarch64/
Dbench-utils.h239 vixl::aarch64::VRegister PickS() { return PickV(vixl::aarch64::kSRegSize); } in PickS()
Dbench-utils.cc93 return ((entropy & 1) == 0) ? kSRegSize : kDRegSize; in PickFPSize()
/third_party/node/deps/v8/src/codegen/arm64/
Dinstructions-arm64.cc172 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size."); in CalcLSPairDataSize()
Dconstants-arm64.h55 const int kSRegSize = kSRegSizeInBits >> 3; variable