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Searched refs:kZRegBitsPerPRegBit (Results 1 – 9 of 9) sorted by relevance

/third_party/vixl/test/aarch64/
Dtest-utils-aarch64.h192 VIXL_ASSERT(lane < GetSVELaneCount(p_bits_per_lane * kZRegBitsPerPRegBit)); in preg_lane()
225 VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0); in GetSVELane()
227 reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit, in GetSVELane()
Dtest-utils-aarch64.cc391 VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0); in EqualSVELane()
392 unsigned p_bits_per_lane = reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit; in EqualSVELane()
Dtest-assembler-sve-aarch64.cc123 int p_bits_per_lane = pd.GetLaneSizeInBits() / kZRegBitsPerPRegBit; in Initialise()
5289 VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0); in TEST_SVE()
5290 uint64_t pl = vl / kZRegBitsPerPRegBit; in TEST_SVE()
5447 VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0); in TEST_SVE()
5448 uint64_t pl = vl / kZRegBitsPerPRegBit; in TEST_SVE()
5550 VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0); in TEST_SVE()
5551 uint64_t pl = vl / kZRegBitsPerPRegBit; in TEST_SVE()
6935 VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0); in TEST_SVE()
6936 int pl = vl / kZRegBitsPerPRegBit; in TEST_SVE()
14091 int pl = config->sve_vl_in_bits() / kZRegBitsPerPRegBit; in TEST_SVE()
Dtest-trace-aarch64.cc2974 const int pl_in_bits = vl_in_bits / kZRegBitsPerPRegBit; in TraceTestHelper()
/third_party/vixl/src/aarch64/
Dinstructions-aarch64.h133 const unsigned kZRegBitsPerPRegBit = kBitsPerByte; variable
135 const unsigned kPRegMinSize = kZRegMinSize / kZRegBitsPerPRegBit;
139 const unsigned kPRegMaxSize = kZRegMaxSize / kZRegBitsPerPRegBit;
Dmacro-assembler-sve-aarch64.cc204 if ((multiplier % kZRegBitsPerPRegBit) == 0) { in Addpl()
205 Addvl(xd, xn, multiplier / kZRegBitsPerPRegBit); in Addpl()
336 VIXL_ASSERT((kZRegBitsPerPRegBit % vl_divisor) == 0); in CalculateSVEAddress()
337 Addpl(xd, base, offset * (kZRegBitsPerPRegBit / vl_divisor)); in CalculateSVEAddress()
Dsimulator-aarch64.h2724 VIXL_ASSERT((GetVectorLengthInBits() % kZRegBitsPerPRegBit) == 0);
2725 return GetVectorLengthInBits() / kZRegBitsPerPRegBit;
2728 VIXL_ASSERT((GetVectorLengthInBytes() % kZRegBitsPerPRegBit) == 0);
2729 return GetVectorLengthInBytes() / kZRegBitsPerPRegBit;
Dlogic-aarch64.cc1625 LaneSizeInBitsFromFormat(vform) / kZRegBitsPerPRegBit; in sel()
Dsimulator-aarch64.cc1574 int print_size_in_bits = kQRegSize / kZRegBitsPerPRegBit; in Simulator()