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Searched refs:lane0 (Results 1 – 7 of 7) sorted by relevance

/third_party/node/deps/v8/src/wasm/
Dsimd-shuffle.h41 uint8_t lane0[kBytesPerLane]; in TryMatchSplat() local
42 lane0[0] = shuffle[0]; in TryMatchSplat()
43 if (lane0[0] % kBytesPerLane != 0) return false; in TryMatchSplat()
45 lane0[i] = shuffle[i]; in TryMatchSplat()
46 if (lane0[i] != lane0[0] + i) return false; in TryMatchSplat()
51 if (lane0[j] != shuffle[i * kBytesPerLane + j]) return false; in TryMatchSplat()
54 *index = lane0[0] / kBytesPerLane; in TryMatchSplat()
/third_party/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc7345 uint8_t lane0 = 1 - (3 * i); in TEST_SVE() local
7347 MemoryWrite(middle, 0, (i * reg_count) + 0, lane0); in TEST_SVE()
7355 uint16_t lane0 = -2 + (5 * i); in TEST_SVE() local
7357 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0); in TEST_SVE()
7365 uint32_t lane0 = 3 - (7 * i); in TEST_SVE() local
7367 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0); in TEST_SVE()
7375 uint64_t lane0 = -7 + (3 * i); in TEST_SVE() local
7377 MemoryWrite(middle, offset, (i * reg_count) + 0, lane0); in TEST_SVE()
7516 uint8_t lane0 = -4 + (11 * i); in TEST_SVE() local
7518 MemoryWrite(middle, 0, (i * reg_count) + 0, lane0); in TEST_SVE()
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/third_party/mesa3d/src/amd/llvm/
Dac_llvm_build.h531 LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned lane0,
Dac_llvm_build.c3269 static inline enum dpp_ctrl dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, in dpp_quad_perm() argument
3272 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); in dpp_quad_perm()
3273 return _dpp_quad_perm | lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6); in dpp_quad_perm()
4162 LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned lane0, in ac_build_quad_swizzle() argument
4165 unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3); in ac_build_quad_swizzle()
/third_party/node/deps/simdutf/
Dsimdutf.cpp16413 simdutf_really_inline __m512i expand_and_identify(__m512i lane0, __m512i lane1, int &count) { in expand_and_identify() argument
16414 const __m512i merged = _mm512_mask_mov_epi32(lane0, 0x1000, lane1); in expand_and_identify()
16638 const __m512i lane0 = broadcast_epi128<0>(utf8); in valid_utf8_to_fixed_length() local
16641 __m512i vec0 = expand_and_identify(lane0, lane1, valid_count0); in valid_utf8_to_fixed_length()
16687 const __m512i lane0 = broadcast_epi128<0>(utf8); in valid_utf8_to_fixed_length() local
16690 __m512i vec0 = expand_and_identify(lane0, lane1, valid_count0); in valid_utf8_to_fixed_length()
16936 const __m512i lane0 = broadcast_epi128<0>(utf8); in validating_utf8_to_fixed_length() local
16939 __m512i vec0 = expand_and_identify(lane0, lane1, valid_count0); in validating_utf8_to_fixed_length()
16986 const __m512i lane0 = broadcast_epi128<0>(utf8); in validating_utf8_to_fixed_length() local
16989 __m512i vec0 = expand_and_identify(lane0, lane1, valid_count0); in validating_utf8_to_fixed_length()
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/third_party/mesa3d/docs/relnotes/
D21.0.0.rst320 - pan/bi: Use consistent naming of lane/lane0
D21.2.0.rst2753 - pan/bi: Replace lane0 modifier with lane_dest for load instructions