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Searched refs:lane_size_in_bits (Results 1 – 10 of 10) sorted by relevance

/third_party/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc371 static void MlaMlsHelper(Test* config, unsigned lane_size_in_bits) { in MlaMlsHelper() argument
380 ZRegister zd = z0.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
381 ZRegister za = z1.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
382 ZRegister zn = z2.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
383 ZRegister zm = z3.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
396 Initialise(&masm, p0.WithLaneSize(lane_size_in_bits), p0_inputs); in MlaMlsHelper()
397 Initialise(&masm, p1.WithLaneSize(lane_size_in_bits), p1_inputs); in MlaMlsHelper()
398 Initialise(&masm, p2.WithLaneSize(lane_size_in_bits), p2_inputs); in MlaMlsHelper()
399 Initialise(&masm, p3.WithLaneSize(lane_size_in_bits), p3_inputs); in MlaMlsHelper()
403 ZRegister mla_da_result = z10.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
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Dtest-utils-aarch64.h205 inline int GetSVELaneCount(int lane_size_in_bits) const { in GetSVELaneCount() argument
206 VIXL_ASSERT(lane_size_in_bits > 0); in GetSVELaneCount()
207 VIXL_ASSERT((dump_.vl_ % lane_size_in_bits) == 0); in GetSVELaneCount()
208 uint64_t count = dump_.vl_ / lane_size_in_bits; in GetSVELaneCount()
/third_party/vixl/src/aarch64/
Dinstructions-aarch64.cc629 int lane_size_in_bits = 1 << (lane_size_in_bytes_log2 + 3); in GetSVEImmLogical() local
630 return DecodeImmBitMask(n, imm_s, imm_r, lane_size_in_bits); in GetSVEImmLogical()
1141 VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits) { in ScalarFormatFromLaneSize() argument
1142 switch (lane_size_in_bits) { in ScalarFormatFromLaneSize()
1192 VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits) { in SVEFormatFromLaneSizeInBits() argument
1193 switch (lane_size_in_bits) { in SVEFormatFromLaneSizeInBits()
1199 return SVEFormatFromLaneSizeInBytes(lane_size_in_bits / kBitsPerByte); in SVEFormatFromLaneSizeInBits()
Dregisters-aarch64.h632 explicit ZRegister(int code, int lane_size_in_bits = kUnknownSize) in VIXL_DECLARE_REGISTER_COMMON()
636 EncodeSizeInBits(lane_size_in_bits)) { in VIXL_DECLARE_REGISTER_COMMON()
720 PRegisterWithLaneSize(int code, int lane_size_in_bits) in VIXL_DECLARE_REGISTER_COMMON()
721 : PRegister(code, EncodeSizeInBits(lane_size_in_bits)) { in VIXL_DECLARE_REGISTER_COMMON()
Dinstructions-aarch64.h712 VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits);
716 VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits);
Dlogic-aarch64.cc886 int lane_size_in_bits) const { in PolynomialMult()
887 VIXL_ASSERT(static_cast<unsigned>(lane_size_in_bits) <= kSRegSize); in PolynomialMult()
888 VIXL_ASSERT(IsUintN(lane_size_in_bits, op1)); in PolynomialMult()
889 VIXL_ASSERT(IsUintN(lane_size_in_bits, op2)); in PolynomialMult()
891 for (int i = 0; i < lane_size_in_bits; ++i) { in PolynomialMult()
1791 int lane_size_in_bits = LaneSizeInBitsFromFormat(vform); in cls() local
1798 result[i] = CountLeadingSignBits(src.Int(vform, i), lane_size_in_bits); in cls()
1812 int lane_size_in_bits = LaneSizeInBitsFromFormat(vform); in clz() local
1819 result[i] = CountLeadingZeros(src.Uint(vform, i), lane_size_in_bits); in clz()
1845 int lane_size_in_bits = LaneSizeInBitsFromFormat(vform); in cnt() local
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Dassembler-aarch64.cc4946 int lane_size_in_bits = vn.GetLaneSizeInBits(); in NEONShiftLeftImmediate() local
4947 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits)); in NEONShiftLeftImmediate()
4948 NEONShiftImmediate(vd, vn, op, (lane_size_in_bits + shift) << 16); in NEONShiftLeftImmediate()
4956 int lane_size_in_bits = vn.GetLaneSizeInBits(); in NEONShiftRightImmediate() local
4957 VIXL_ASSERT((shift >= 1) && (shift <= lane_size_in_bits)); in NEONShiftRightImmediate()
4958 NEONShiftImmediate(vd, vn, op, ((2 * lane_size_in_bits) - shift) << 16); in NEONShiftRightImmediate()
4966 int lane_size_in_bits = vn.GetLaneSizeInBits(); in NEONShiftImmediateL() local
4967 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits)); in NEONShiftImmediateL()
4968 int immh_immb = (lane_size_in_bits + shift) << 16; in NEONShiftImmediateL()
4984 int lane_size_in_bits = vd.GetLaneSizeInBits(); in NEONShiftImmediateN() local
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Dassembler-sve-aarch64.cc368 Instr Assembler::EncodeSVEShiftLeftImmediate(int shift, int lane_size_in_bits) { in EncodeSVEShiftLeftImmediate() argument
369 VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits)); in EncodeSVEShiftLeftImmediate()
370 return lane_size_in_bits + shift; in EncodeSVEShiftLeftImmediate()
374 int lane_size_in_bits) { in EncodeSVEShiftRightImmediate() argument
375 VIXL_ASSERT((shift > 0) && (shift <= lane_size_in_bits)); in EncodeSVEShiftRightImmediate()
376 return (2 * lane_size_in_bits) - shift; in EncodeSVEShiftRightImmediate()
Dassembler-aarch64.h7846 Instr EncodeSVEShiftLeftImmediate(int shift, int lane_size_in_bits);
7848 Instr EncodeSVEShiftRightImmediate(int shift, int lane_size_in_bits);
Dsimulator-aarch64.h2929 int lane_size_in_bits) const;