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Searched refs:lower_simd_width (Results 1 – 10 of 10) sorted by relevance

/third_party/mesa3d/docs/relnotes/
D18.1.4.rst74 - intel/fs: Split instructions low to high in lower_simd_width
D19.3.3.rst104 - intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().
D18.3.2.rst150 - intel/fs: Fix bug in lower_simd_width while splitting an instruction
D19.0.0.rst1008 - intel/fs: Fix bug in lower_simd_width while splitting an instruction
D20.0.0.rst1291 - intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().
D21.3.0.rst3758 - intel/compiler: Handle ternary add in lower_simd_width
/third_party/mesa3d/src/intel/compiler/
Dbrw_vec4.h161 bool lower_simd_width();
Dbrw_fs.h199 bool lower_simd_width();
Dbrw_vec4.cpp1957 vec4_visitor::lower_simd_width() in lower_simd_width() function in brw::vec4_visitor
2454 if (OPT(lower_simd_width)) { in run()
Dbrw_fs.cpp5281 fs_visitor::lower_simd_width() in lower_simd_width() function in fs_visitor
6121 OPT(lower_simd_width); in optimize()
6160 OPT(lower_simd_width); in optimize()
6188 OPT(lower_simd_width); in optimize()