| /third_party/node/deps/v8/src/compiler/ |
| D | simplified-lowering.cc | 714 void RunLowerPhase(SimplifiedLowering* lowering) { in RunLowerPhase() argument
726 VisitNode<LOWER>(node, info->truncation(), lowering); in RunLowerPhase()
783 void Run(SimplifiedLowering* lowering) { in Run() argument
787 RunLowerPhase(lowering); in Run()
790 RunVerifyPhase(lowering->info_); in Run()
1160 SimplifiedLowering* lowering) { in VisitSelect() argument
1172 ChangeOp(node, lowering->common()->Select(output, p.hint())); in VisitSelect()
1185 SimplifiedLowering* lowering) { in VisitPhi() argument
1196 ChangeOp(node, lowering->common()->Phi(output, values)); in VisitPhi()
1209 void VisitObjectIs(Node* node, Type type, SimplifiedLowering* lowering) { in VisitObjectIs() argument
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| D | bytecode-graph-builder.cc | 1587 JSTypeHintLowering::LoweringResult lowering = in VisitStaInArrayLiteral() local
1589 if (lowering.IsExit()) return; in VisitStaInArrayLiteral()
1592 if (lowering.IsSideEffectFree()) { in VisitStaInArrayLiteral()
1593 node = lowering.value(); in VisitStaInArrayLiteral()
1595 DCHECK(!lowering.Changed()); in VisitStaInArrayLiteral()
1616 JSTypeHintLowering::LoweringResult lowering = in VisitDefineKeyedOwnPropertyInLiteral() local
1618 if (lowering.IsExit()) return; in VisitDefineKeyedOwnPropertyInLiteral()
1621 if (lowering.IsSideEffectFree()) { in VisitDefineKeyedOwnPropertyInLiteral()
1622 node = lowering.value(); in VisitDefineKeyedOwnPropertyInLiteral()
1624 DCHECK(!lowering.Changed()); in VisitDefineKeyedOwnPropertyInLiteral()
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| D | OWNERS | 13 per-file int64-lowering.*=ahaas@chromium.org
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| /third_party/mesa3d/src/compiler/glsl/ |
| D | lower_instructions.cpp | 132 #define lowering(x) (this->lower & x) macro
304 if (!lowering(INSERT_TO_SHIFTS)) { in ldexp_to_arith()
373 if (lowering(DFREXP_DLDEXP_TO_ARITH)) in dldexp_to_arith()
1284 if (lowering(CARRY_TO_ARITH)) in _carry()
1456 if (lowering(SUB_TO_ADD_NEG)) in visit_leave()
1461 if (lowering(LDEXP_TO_ARITH) && ir->type->is_float()) in visit_leave()
1463 if (lowering(DFREXP_DLDEXP_TO_ARITH) && ir->type->is_double()) in visit_leave()
1468 if (lowering(DFREXP_DLDEXP_TO_ARITH) && ir->operands[0]->type->is_double()) in visit_leave()
1473 if (lowering(DFREXP_DLDEXP_TO_ARITH) && ir->operands[0]->type->is_double()) in visit_leave()
1478 if (lowering(CARRY_TO_ARITH)) in visit_leave()
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| D | lower_int64.cpp | 132 #define lowering(x) (this->lower & x) macro
357 if (lowering(DIV64)) { in handle_rvalue()
367 if (lowering(MOD64)) { in handle_rvalue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/docs/ |
| D | DESIGN.rst | 69 | | Phi lowering (simple) |
71 | Target lowering | Target lowering |
77 | Phi lowering (advanced) | |
298 - Assign: a simple ``A=B`` assignment. This is useful for e.g. lowering Phi
299 instructions to non-SSA assignments, before lowering to machine code.
353 example, lowering an operation like ``x=cc?y:z`` may be done using x86's
375 Overview of lowering
388 independently, though the target lowering is allowed to look ahead in the
431 debugging -- during translation, it tends to expose errors in the basic lowering
434 is a fundamental problem in the basic lowering, or an error in another
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| D | LOWERING.rst | 1 Target-specific lowering in ICE
17 happens after target-specific lowering, so during lowering we generally don't
35 The recommended ICE lowering strategy is to generate extra assignment
61 low-level lowering code that accomplishes this looks something like::
90 (An older version of ICE allowed the lowering code to provide a register
165 only one or the other is needed in the lowering.
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| D | REGALLOC.rst | 27 convergence, delayed phi lowering, and local live range splitting).
40 - Basic lowering is done before register allocation. Lowering is the process of
44 which case the lowering is relatively simple. But if the lowered instruction
87 - The main register allocation is done before phi lowering, because phi lowering
236 Because Subzero does register allocation after basic lowering, the lowering has
301 Delayed Phi lowering
309 Unfortunately, simple phi lowering imposes an arbitrary ordering on the
318 A straightforward lowering might yield::
329 lowering, followed by phi lowering, and finally a special register allocation
332 Phi lowering considers the phi operands separately for each predecessor edge,
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| D | README.rst | 192 * Simple Phi lowering before target lowering, by generating temporaries and
207 * Advanced phi lowering after target lowering and global register allocation,
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/ |
| D | DESIGN.rst | 69 | | Phi lowering (simple) |
71 | Target lowering | Target lowering |
77 | Phi lowering (advanced) | |
298 - Assign: a simple ``A=B`` assignment. This is useful for e.g. lowering Phi
299 instructions to non-SSA assignments, before lowering to machine code.
353 example, lowering an operation like ``x=cc?y:z`` may be done using x86's
375 Overview of lowering
388 independently, though the target lowering is allowed to look ahead in the
431 debugging -- during translation, it tends to expose errors in the basic lowering
434 is a fundamental problem in the basic lowering, or an error in another
[all …]
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| D | README.rst | 192 * Simple Phi lowering before target lowering, by generating temporaries and
207 * Advanced phi lowering after target lowering and global register allocation,
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.def | 10 // This file defines certain patterns for lowering to ARM32 target
18 // Patterns for lowering fcmp. These are expected to be used in the following
54 // Patterns for lowering icmp.
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| D | IceTargetLoweringMIPS32.def | 10 // This file defines certain patterns for lowering to MIPS32 target
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| /third_party/mesa3d/docs/relnotes/ |
| D | 19.1.5.rst | 46 - radv: Do non-uniform lowering before bool lowering.
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| D | 19.1.6.rst | 58 lowering is enabled
59 - intel/compiler: Request bitfield_reverse lowering on pre-Gen7
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| D | 17.2.6.rst | 68 - cherry-ignore: intel/nir: Use the correct indirect lowering masks in
71 MUL lowering
126 - intel/fs: Fix integer multiplication lowering for src/dst hazards
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| D | 17.2.5.rst | 47 - cherry-ignore: radv: copy indirect lowering settings from radeonsi
117 - radv: copy indirect lowering settings from radeonsi
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| D | 21.2.5.rst | 48 - panfrost: Fix gl_FragColor lowering
95 - anv: fix push constant lowering with bindless shaders
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| D | 10.3.3.rst | 152 - freedreno: add texcoord clamp support to lowering
155 - freedreno/lowering: fix token calculation for lowering
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| D | 12.0.6.rst | 77 - nir/lower_tex: Add support for lowering coordinate offsets
78 - i965/nir: Enable NIR lowering of txf and rect offsets
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| D | 21.3.1.rst | 49 - ir3/lower_pcopy: Fix shr.b illegal copy lowering
84 - intel/fs: fix shader call lowering pass
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCPseudoLowering.inc | 3 |* Pseudo-instruction MC lowering Source Fragment *|
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| /third_party/mesa3d/docs/nir/ |
| D | tex.rst | 57 Texture instruction lowering
61 texture operations, NIR provides a quite powerful lowering pass which is able
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| D | index.rst | 7 functions, optimization passes, and lowering passes for building a compiler
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Relocation.txt | 10 1. Code for lowering addresses references to machine dependent code is
12 is called by the relocation model specific lowering function, using
|