| /third_party/mesa3d/src/compiler/nir/tests/ |
| D | ssa_def_bits_used_tests.cpp | 81 nir_ssa_def *src0 = nir_imm_ivec4(&bld, in TEST_F()
110 nir_ssa_def *src0 = nir_imm_ivec4(&bld, in TEST_F()
141 nir_ssa_def *src1 = nir_imm_ivec4(&bld, in TEST_F()
172 nir_ssa_def *src1 = nir_imm_ivec4(&bld, in TEST_F()
203 nir_ssa_def *src1 = nir_imm_ivec4(&bld, in TEST_F()
234 nir_ssa_def *src1 = nir_imm_ivec4(&bld, in TEST_F()
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| D | vars_tests.cpp | 2001 nir_store_var(b, out, nir_imm_ivec4(b, 0, 0, 0, 0), 1 << 0); in TEST_F()
2002 nir_store_var(b, out, nir_imm_ivec4(b, 1, 1, 1, 1), 1 << 1); in TEST_F()
2003 nir_store_var_volatile(b, out, nir_imm_ivec4(b, -1, -2, -3, -4), 0xf); in TEST_F()
2004 nir_store_var(b, out, nir_imm_ivec4(b, 2, 2, 2, 2), 1 << 2); in TEST_F()
2005 nir_store_var(b, out, nir_imm_ivec4(b, 3, 3, 3, 3), 1 << 3); in TEST_F()
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| /third_party/mesa3d/src/panfrost/util/ |
| D | pan_lower_framebuffer.c | 228 nir_ssa_def *shifts = nir_imm_ivec4(b, 8 - x, 8 - y, 8 - z, 8 - w); in pan_pack_norm()
267 nir_ssa_def *top8 = nir_ushr(b, s, nir_imm_ivec4(b, 0x2, 0x2, 0x2, 0x2)); in pan_pack_unorm_1010102()
270 nir_ssa_def *bottom2 = nir_iand(b, s, nir_imm_ivec4(b, 0x3, 0x3, 0x3, 0x3)); in pan_pack_unorm_1010102()
294 v = nir_imin(b, v, nir_imm_ivec4(b, 511, 511, 511, 1)); in pan_pack_int_1010102()
295 v = nir_imax(b, v, nir_imm_ivec4(b, -512, -512, -512, -2)); in pan_pack_int_1010102()
297 v = nir_umin(b, v, nir_imm_ivec4(b, 1023, 1023, 1023, 3)); in pan_pack_int_1010102()
300 v = nir_ishl(b, v, nir_imm_ivec4(b, 0, 10, 20, 30)); in pan_pack_int_1010102()
317 v = nir_ishl(b, v, nir_imm_ivec4(b, 22, 12, 2, 0)); in pan_unpack_int_1010102()
320 v = nir_ishr(b, v, nir_imm_ivec4(b, 22, 22, 22, 30)); in pan_unpack_int_1010102()
322 v = nir_ushr(b, v, nir_imm_ivec4(b, 22, 22, 22, 30)); in pan_unpack_int_1010102()
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| D | pan_lower_writeout.c | 65 nir_ssa_def *zero4 = nir_imm_ivec4(b, 0, 0, 0, 0); in pan_nir_emit_combined_store()
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| /third_party/mesa3d/src/microsoft/compiler/ |
| D | dxil_nir_lower_vs_vertex_conversion.c | 61 nir_ssa_def *rshift = nir_imm_ivec4(b, 22, 22, 22, 30); in from_10_10_10_2_scaled()
92 return nir_imm_ivec4(b, 22, 12, 2, 0); in lshift_rgba()
98 return nir_imm_ivec4(b, 2, 12, 22, 0); in lshift_bgra()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir_attribute_workarounds.c | 70 nir_ssa_def *shift = nir_imm_ivec4(b, 22, 22, 22, 30); in apply_attr_wa_instr()
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| D | brw_nir_rt_builder.h | 494 nir_ssa_def *zero = nir_imm_ivec4(b, 0, 0, 0, 0); in brw_nir_memclear_global()
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_blend.c | 170 return nir_imm_ivec4(b, 0, 0, 0, 0); in nir_logicop_func()
200 return nir_imm_ivec4(b, ~0, ~0, ~0, ~0); in nir_logicop_func()
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| D | nir_builder.h | 341 nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w) in nir_imm_ivec4() function
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| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_pbo_compute.c | 495 nir_ssa_def *one = nir_imm_ivec4(b, 1, 0, 0, 0); in clamp_and_mask()
496 nir_ssa_def *two = nir_imm_ivec4(b, 1, 1, 0, 0); in clamp_and_mask()
497 nir_ssa_def *three = nir_imm_ivec4(b, 1, 1, 1, 0); in clamp_and_mask()
498 nir_ssa_def *four = nir_imm_ivec4(b, 1, 1, 1, 1); in clamp_and_mask()
615 nir_ssa_def *bsize = nir_imm_ivec4(&b, in create_conversion_shader()
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_nir_lower_tess_io.cpp | 162 case 4: return nir_imm_ivec4(b, 0, 4, 8, 12); in load_offset_group()
174 auto full_mask = nir_imm_ivec4(b, 0, 4, 8, 12); in load_offset_group_from_mask()
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| D | sfn_nir.cpp | 451 addr = nir_iadd(&b, addr, nir_imm_ivec4(&b, 0, 4, 8, 12)); in r600_lower_shared_io_impl()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_rt_common.c | 92 nir_imm_ivec4(b, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu), 0xf); in intersect_ray_amd_software_box()
432 return nir_imm_ivec4( in create_bvh_descriptor()
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| D | radv_nir_apply_pipeline_layout.c | 259 …return nir_imm_ivec4(b, samplers[constant_index * 4 + 0] & dword0_mask, samplers[constant_index * … in get_sampler_desc()
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| D | radv_meta_decompress.c | 57 nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1], in build_expand_depth_stencil_compute_shader()
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| D | radv_meta.c | 847 nir_imm_ivec4(b, b->shader->info.workgroup_size[0], b->shader->info.workgroup_size[1], in get_global_ids()
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| D | radv_acceleration_structure.c | 1684 nir_imm_ivec4(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1], in build_copy_shader()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shaderlib_nir.c | 212 nir_channels(&b, nir_imm_ivec4(&b, tex->surface.u.gfx9.color.dcc_block_width, in gfx9_create_clear_dcc_msaa_cs()
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