/third_party/mesa3d/src/amd/vulkan/ |
D | radv_rt_common.c | 407 nir_test_mask(b, geometry_id_and_flags, VK_GEOMETRY_OPAQUE_BIT_KHR << 28); in hit_is_opaque() 409 nir_test_mask(b, sbt_offset_and_flags, VK_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT_KHR << 24); in hit_is_opaque() 411 nir_test_mask(b, sbt_offset_and_flags, VK_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT_KHR << 24); in hit_is_opaque() 417 nir_ssa_def *ray_force_opaque = nir_test_mask(b, flags, SpvRayFlagsOpaqueKHRMask); in hit_is_opaque() 418 nir_ssa_def *ray_force_non_opaque = nir_test_mask(b, flags, SpvRayFlagsNoOpaqueKHRMask); in hit_is_opaque()
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D | radv_query.c | 49 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)); in radv_store_availability() 51 nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_64_BIT)); in radv_store_availability() 172 nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); in build_occlusion_query_shader() 175 nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), in build_occlusion_query_shader() 278 nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); in build_pipeline_statistics_query_shader() 290 nir_push_if(&b, nir_test_mask(&b, stats_mask, BITFIELD64_BIT(i))); in build_pipeline_statistics_query_shader() 339 nir_push_if(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT)); in build_pipeline_statistics_query_shader() 442 nir_test_mask(&b, nir_iand(&b, avails[0], avails[1]), 0x80000000); in build_tfb_query_shader() 468 nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); in build_tfb_query_shader() 473 nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), in build_tfb_query_shader() [all …]
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D | radv_nir_lower_ray_queries.c | 302 nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); in insert_terminate_on_first_hit() 514 nir_test_mask(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), in insert_traversal_triangle_case() 520 b, nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsSkipTrianglesKHRMask)); in insert_traversal_triangle_case() 531 nir_test_mask(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), in insert_traversal_triangle_case() 597 b, nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsSkipAABBsKHRMask)); in insert_traversal_aabb_case()
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D | radv_pipeline_rt.c | 1127 nir_test_mask(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), in insert_traversal_triangle_case() 1132 nir_inot(b, nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsSkipTrianglesKHRMask)); in insert_traversal_triangle_case() 1143 nir_test_mask(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), in insert_traversal_triangle_case() 1226 nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); in insert_traversal_triangle_case() 1254 nir_inot(b, nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsSkipAABBsKHRMask)); in insert_traversal_aabb_case() 1371 nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); in insert_traversal_aabb_case() 1582 nir_test_mask(&b, nir_load_var(&b, vars.flags), in build_traversal_shader()
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D | radv_device_generated_commands.c | 246 nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID); in dgc_emit_userdata_vertex() 248 nir_test_mask(b, vtx_base_sgpr, DGC_USES_BASEINSTANCE); in dgc_emit_userdata_vertex() 431 …nir_ssa_def *dyn_stride = nir_test_mask(&b, nir_channel(&b, vbo_over_data, 0), DGC_DYNAMIC_STRIDE); in build_dgc_prepare_shader() 438 nir_test_mask(&b, nir_channel(&b, vbo_over_data, 0), 1u << 31); in build_dgc_prepare_shader() 534 nir_test_mask(&b, load_param8(&b, vbo_cnt), DGC_DYNAMIC_VERTEX_INPUT); in build_dgc_prepare_shader()
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D | radv_meta_etc_decode.c | 276 nir_ssa_def *flip = nir_test_mask(&b, color_y, 1); in build_shader() 284 nir_iand(&b, alpha_bits_1, nir_inot(&b, nir_test_mask(&b, color_y, 2))); in build_shader() 317 &b, nir_iand(&b, nir_inot(&b, alpha_bits_1), nir_inot(&b, nir_test_mask(&b, color_y, 2)))); in build_shader()
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D | radv_nir_lower_abi.c | 57 return nir_test_mask(b, settings, mask); in nggc_bool_setting()
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/third_party/mesa3d/src/microsoft/vulkan/ |
D | dzn_nir.c | 414 index_val = nir_bcsel(&b, nir_test_mask(&b, old_index_offset, 0x2), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader() 435 index12 = nir_bcsel(&b, nir_test_mask(&b, old_index_offset, 0x2), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader() 516 old_index0 = nir_bcsel(&b, nir_test_mask(&b, old_index0_offset, 0x2), in dzn_nir_triangle_fan_rewrite_index_shader() 532 old_index12 = nir_bcsel(&b, nir_test_mask(&b, old_index1_offset, 0x2), in dzn_nir_triangle_fan_rewrite_index_shader()
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/third_party/mesa3d/src/intel/compiler/ |
D | brw_nir_rt.c | 228 nir_ssa_def *skip_closest_hit = nir_test_mask(b, nir_load_ray_flags(b), in build_terminate_ray() 310 nir_ssa_def *terminate = nir_test_mask(&b, nir_load_ray_flags(&b), in lower_ray_walk_intrinsics()
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/third_party/mesa3d/src/compiler/nir/ |
D | nir_lower_ubo_vec4.c | 145 result = nir_bcsel(b, nir_test_mask(b, byte_offset, 8), in nir_lower_ubo_vec4_lower()
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D | nir_lower_texcoord_replace.c | 126 nir_ssa_def *cond = nir_test_mask(&b, mask, coord_replace); in nir_lower_texcoord_replace_impl()
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D | nir_builder.c | 478 nir_ssa_def *c1cmp = nir_test_mask(b, vertex_id, 1); in nir_gen_rect_vertices()
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D | nir_lower_subgroups.c | 745 return nir_test_mask(b, nir_ushr(b, int_val, idx), 1); in lower_subgroups_instr()
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D | nir_builder.h | 744 nir_test_mask(nir_builder *build, nir_ssa_def *x, uint64_t mask) in nir_test_mask() function
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/third_party/mesa3d/src/microsoft/spirv_to_dxil/ |
D | dxil_spirv_nir.c | 331 nir_ssa_def *flip = nir_test_mask(builder, y_flip_mask, 1); in lower_yz_flip() 338 nir_ssa_def *flip = nir_test_mask(builder, z_flip_mask, 1); in lower_yz_flip()
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/third_party/mesa3d/src/gallium/drivers/d3d12/ |
D | d3d12_nir_passes.c | 417 …nir_push_if(b, nir_test_mask(b, nir_ishl(b, nir_imm_int(b, 1), state->viewport_index), state->view… in invert_depth_impl()
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/third_party/mesa3d/docs/relnotes/ |
D | 22.2.0.rst | 3497 - nir: Add a nir_test_mask helper 3498 - radv: Use nir_test_mask instead of i2b(iand) 3499 - nir: Use nir_test_mask instead of i2b(iand) 3500 - d3d12: Use nir_test_mask instead of i2b(iand) 3501 - intel: Use nir_test_mask instead of i2b(iand) 3502 - microsoft: Use nir_test_mask instead of i2b(iand) 3503 - dozen: Use nir_test_mask instead of i2b(iand)
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