| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_opt_idiv_const.c | 35 return nir_ushr_imm(b, n, util_logbase2_64(d)); in build_udiv()
41 n = nir_ushr_imm(b, n, m.pre_shift); in build_udiv()
46 n = nir_ushr_imm(b, n, m.post_shift); in build_udiv()
81 nir_ssa_def *uq = nir_ushr_imm(b, nir_iabs(b, n), util_logbase2_64(abs_d)); in build_idiv()
97 res = nir_iadd(b, res, nir_ushr_imm(b, res, n->bit_size - 1)); in build_idiv()
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| D | nir_lower_ubo_vec4.c | 91 nir_ssa_def *vec4_offset = nir_ushr_imm(b, byte_offset, 4); in nir_lower_ubo_vec4_lower()
162 nir_ssa_def *chan_vec4_offset = nir_ushr_imm(b, chan_byte_offset, 4); in nir_lower_ubo_vec4_lower()
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| D | nir_format_convert.h | 217 dst_chan[i] = nir_iand(b, nir_ushr_imm(b, nir_channel(b, src, src_idx), in nir_format_bitcast_uvec_unmasked()
430 nir_iadd(b, nir_umax(b, nir_ushr_imm(b, maxu, 23), in nir_format_pack_r9g9b9e5()
458 nir_ushr_imm(b, mantissa, 1)); in nir_format_pack_r9g9b9e5()
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| D | nir_lower_bit_size.c | 79 lowered_dst = nir_ushr_imm(bld, lowered_dst, dst_bit_size); in lower_alu_instr()
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| D | nir_builder.h | 787 nir_ushr_imm(nir_builder *build, nir_ssa_def *x, uint32_t y) in nir_ushr_imm() function
805 return nir_ushr_imm(build, x, ffsll(y) - 1); in nir_udiv_imm()
935 nir_ssa_def *val = nir_ushr_imm(b, src, i * dest_bit_size); in nir_unpack_bits()
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| D | nir_lower_int64.c | 476 carry = nir_ushr_imm(b, tmp, 32); in lower_mul_high64()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_shading_rate_output.c | 98 nir_ior(b, nir_ishl_imm(b, nir_ushr_imm(b, u32_x, 1), 2), in lower_shading_rate_output_instr()
99 nir_ushr_imm(b, u32_y, 1)); in lower_shading_rate_output_instr()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_meta_etc_decode.c | 113 return nir_ior(b, nir_ishl_imm(b, v, 8 - bits), nir_ushr_imm(b, v, bits - (8 - bits))); in etc_extend()
206 nir_vec3(&b, nir_ushr_imm(&b, nir_channel(&b, coord, 0), 2), in build_shader()
207 nir_ushr_imm(&b, nir_channel(&b, coord, 1), 2), nir_channel(&b, coord, 2)); in build_shader()
277 nir_ssa_def *subblock = nir_ushr_imm( in build_shader()
379 nir_iand_imm(&b, nir_ushr_imm(&b, color_y, 20), 1)); in build_shader()
381 nir_iand_imm(&b, nir_ushr_imm(&b, color_y, 16), 8)); in build_shader()
410 nir_iand_imm(&b, nir_ushr_imm(&b, color_y, 18), 0x40)); in build_shader()
413 nir_ior(&b, nir_iand_imm(&b, nir_ushr_imm(&b, color_y, 11), 0x20), in build_shader()
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| D | radv_meta_copy_vrs_htile.c | 102 nir_ssa_def *x_rate = nir_ushr_imm(&b, nir_channel(&b, &tex->dest.ssa, 0), 2); in build_copy_vrs_htile_shader()
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| D | radv_device_generated_commands.c | 325 nir_ssa_def *len = nir_ushr_imm(b, packet_size, 2); in build_dgc_buffer_tail()
576 nir_ssa_def *const_copy_words = nir_ushr_imm(&b, const_copy_size, 2); in build_dgc_prepare_shader()
896 cnt = nir_ushr_imm(&b, cnt, 2); in build_dgc_prepare_shader()
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| D | radv_acceleration_structure.c | 1261 nir_iadd_imm(&b, nir_ushr_imm(&b, node_offset, 3), radv_bvh_node_triangle); in build_leaf_shader()
1273 nir_ssa_def *node_id = nir_iadd_imm(&b, nir_ushr_imm(&b, node_offset, 3), radv_bvh_node_aabb); in build_leaf_shader()
1334 nir_iadd_imm(&b, nir_ushr_imm(&b, node_offset, 3), radv_bvh_node_instance); in build_leaf_shader()
1649 nir_iadd_imm(&b, nir_ushr_imm(&b, node_offset, 3), radv_bvh_node_internal); in build_internal_shader()
1837 nir_ssa_def *instance_id = nir_ushr_imm(&b, instance_offset, 7); in build_copy_shader()
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| D | radv_rt_common.c | 344 nir_ssa_def *node = nir_ushr_imm(b, addr, 3); in build_addr_to_node()
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| D | radv_nir_lower_ray_queries.c | 723 nir_ssa_def *instance_mask = nir_ushr_imm(b, instance_and_mask, 24); in lower_rq_proceed()
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| D | radv_query.c | 280 nir_ssa_def *elem_count = nir_ushr_imm(&b, stats_mask, 16); in build_pipeline_statistics_query_shader()
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| D | radv_pipeline_rt.c | 1494 nir_ssa_def *instance_mask = nir_ushr_imm(&b, instance_and_mask, 24); in build_traversal_shader()
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| /third_party/mesa3d/src/microsoft/vulkan/ |
| D | dzn_nir.c | 415 nir_ushr_imm(&b, index_val, 16), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
431 nir_ushr_imm(&b, nir_channel(&b, index12, 0), 16), in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
517 nir_ushr_imm(&b, old_index0, 16), in dzn_nir_triangle_fan_rewrite_index_shader()
528 nir_ushr_imm(&b, nir_channel(&b, old_index12, 0), 16), in dzn_nir_triangle_fan_rewrite_index_shader()
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| /third_party/mesa3d/src/panfrost/lib/ |
| D | pan_indirect_draw.c | 459 nir_ssa_def *half_div64 = nir_u2u64(b, nir_ushr_imm(b, div, 1)); in split_div()
798 nir_ishl(b, nir_ushr_imm(b, base, 1), nir_imm_int(b, 5))); in get_padded_count()
888 val = nir_ushr_imm(b, val, shift); in get_instance_size()
913 val = nir_ushr_imm(b, val, shift); in get_instance_size()
1061 nir_ssa_def *data = nir_ushr_imm(b, val, i * 8); in get_index_min_max()
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| D | pan_indirect_dispatch.c | 119 nir_ssa_def *num_wg_x_split = nir_iand_imm(&b, nir_ushr_imm(&b, split, 10), 0x3f); in GENX()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.c | 3153 v = nir_ixor(b, v, nir_iand(b, nir_ushr_imm(b, bits, u_bit_scan(&mask)), one)); in gfx10_nir_meta_addr_from_coord()
3163 nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2); in gfx10_nir_meta_addr_from_coord()
3164 nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2); in gfx10_nir_meta_addr_from_coord()
3165 nir_ssa_def *pb = nir_ushr_imm(b, meta_pitch, meta_block_width_log2); in gfx10_nir_meta_addr_from_coord()
3197 nir_ssa_def *pitchInBlock = nir_ushr_imm(b, meta_pitch, meta_block_width_log2); in gfx9_nir_meta_addr_from_coord()
3198 nir_ssa_def *sliceSizeInBlock = nir_imul(b, nir_ushr_imm(b, meta_height, meta_block_height_log2), in gfx9_nir_meta_addr_from_coord()
3201 nir_ssa_def *xb = nir_ushr_imm(b, x, meta_block_width_log2); in gfx9_nir_meta_addr_from_coord()
3202 nir_ssa_def *yb = nir_ushr_imm(b, y, meta_block_height_log2); in gfx9_nir_meta_addr_from_coord()
3203 nir_ssa_def *zb = nir_ushr_imm(b, z, meta_block_depth_log2); in gfx9_nir_meta_addr_from_coord()
3223 nir_iand(b, nir_ushr_imm(b, coords[equation->u.gfx9.bit[i].coord[c].dim], in gfx9_nir_meta_addr_from_coord()
[all …]
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| D | ac_nir_lower_ngg.c | 1587 nir_ssa_def *row = nir_ushr_imm(b, out_vtx_idx, 5); in ngg_gs_out_vertex_addr()
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| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_pbo_compute.c | 196 val = nir_ushr_imm(b, val, offset); \
379 nir_ushr_imm(b, src, 8), in swap2()
389 nir_ushr_imm(b, src, 24), in swap4()
392 nir_iand(b, nir_ushr_imm(b, src, 8), nir_imm_int(b, 0xff00)), in swap4()
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| /third_party/mesa3d/src/panfrost/vulkan/ |
| D | panvk_vX_meta_copy.c | 379 nir_ushr_imm(&b, nir_channel(&b, rgb, 1), 3), in panvk_meta_copy_img2img_shader()
391 nir_ushr_imm(&b, nir_channel(&b, rg, 0), 5), in panvk_meta_copy_img2img_shader()
394 nir_ushr_imm(&b, nir_channel(&b, rg, 1), 3)); in panvk_meta_copy_img2img_shader()
926 nir_iand_imm(&b, nir_ushr_imm(&b, texel, 5), BITFIELD_MASK(6)), in panvk_meta_copy_buf2img_shader()
927 nir_iand_imm(&b, nir_ushr_imm(&b, texel, 11), BITFIELD_MASK(5))); in panvk_meta_copy_buf2img_shader()
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| D | panvk_vX_nir_lower_descriptors.c | 428 return nir_u2u32(b, nir_ushr_imm(b, nir_channel(b, desc, 3), 8)); in load_tex_img_samples()
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| /third_party/mesa3d/src/microsoft/spirv_to_dxil/ |
| D | dxil_spirv_nir.c | 326 z_flip_mask = nir_ushr_imm(builder, dyn_yz_flip_mask, DXIL_SPIRV_Z_FLIP_SHIFT); in lower_yz_flip()
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