| /third_party/node/deps/v8/src/interpreter/ |
| D | bytecode-node.h | 30 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
37 SetOperand(0, operand0); in bytecode_()
40 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
48 SetOperand(0, operand0); in bytecode_()
52 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
60 SetOperand(0, operand0); in bytecode_()
65 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
74 SetOperand(0, operand0); in bytecode_()
80 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0,
89 SetOperand(0, operand0); in bytecode_()
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| D | bytecode-array-builder.cc | 207 uint32_t operand0 = static_cast<uint32_t>(src.ToOperand()); in OutputMovRaw() local
210 BytecodeNode::Mov(BytecodeSourceInfo(), operand0, operand1)); in OutputMovRaw()
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| /third_party/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_vgpu10.c | 1173 VGPU10OperandToken0 operand0, in setup_operand0_indexing() argument
1184 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 || in setup_operand0_indexing()
1185 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID || in setup_operand0_indexing()
1186 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID || in setup_operand0_indexing()
1187 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_THREAD_ID || in setup_operand0_indexing()
1188 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP || in setup_operand0_indexing()
1189 operand0.operandType == VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID) { in setup_operand0_indexing()
1192 assert(operand0.selectionMode == 0); in setup_operand0_indexing()
1194 else if (operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT) { in setup_operand0_indexing()
1222 operand0.indexDimension = indexDim; in setup_operand0_indexing()
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| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| D | instruction-selector-ia32.cc | 326 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRROFloat() local
329 selector->Emit(opcode, g.DefineAsRegister(node), operand0, operand1); in VisitRROFloat()
331 selector->Emit(opcode, g.DefineSameAsFirst(node), operand0, operand1); in VisitRROFloat()
355 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRSimd() local
357 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0); in VisitRRSimd()
359 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0); in VisitRRSimd()
374 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRROSimd() local
376 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, in VisitRROSimd()
379 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, in VisitRROSimd()
389 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRRSimd() local
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| /third_party/mesa3d/src/gallium/drivers/zink/nir_to_spirv/ |
| D | spirv_builder.h | 205 SpvId operand0, SpvId operand1);
209 SpvId operand0, SpvId operand1, SpvId operand2);
213 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3);
217 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3,
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| D | spirv_builder.c | 529 SpvId operand0, SpvId operand1) in spirv_builder_emit_binop() argument
536 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_binop()
543 SpvId operand0, SpvId operand1, SpvId operand2) in spirv_builder_emit_triop() argument
550 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_triop()
558 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3) in spirv_builder_emit_quadop() argument
565 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_quadop()
574 SpvId operand0, SpvId operand1, SpvId operand2, SpvId operand3, in spirv_builder_emit_hexop() argument
582 spirv_buffer_emit_word(&b->instructions, operand0); in spirv_builder_emit_hexop()
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | instruction-selector-arm.cc | 2846 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); local
2848 Emit(kArmI64x2SplatI32Pair, g.DefineAsRegister(node), operand0, operand1);
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| /third_party/node/deps/v8/src/compiler/backend/x64/ |
| D | instruction-selector-x64.cc | 3425 InstructionOperand operand0 = IsSupported(AVX) in VISIT_SIMD_QFMOP() local
3428 Emit(kX64I64x2Neg, g.DefineAsRegister(node), operand0); in VISIT_SIMD_QFMOP()
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