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Searched refs:physreg (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/freedreno/ir3/
Dir3_ra.c794 struct ir3_register *reg, physreg_t physreg, bool is_source) in get_reg_specified() argument
799 physreg + i)) in get_reg_specified()
804 check_dst_overlap(ctx, file, reg, physreg, physreg + reg_size(reg))) in get_reg_specified()
817 struct ir3_register *reg, physreg_t physreg, in try_evict_regs() argument
828 BITSET_CLEAR(available_to_evict, physreg + i); in try_evict_regs()
829 BITSET_CLEAR(available, physreg + i); in try_evict_regs()
834 for (struct ra_interval *conflicting = ra_file_search_right(file, physreg), in try_evict_regs()
837 conflicting->physreg_start < physreg + reg_size(reg); in try_evict_regs()
1222 physreg_t physreg; in compress_regs_left() local
1226 physreg = dst_reg; in compress_regs_left()
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Dir3_ra.h56 ra_physreg_to_num(physreg_t physreg, unsigned flags) in ra_physreg_to_num() argument
59 physreg /= 2; in ra_physreg_to_num()
61 physreg += 48 * 4; in ra_physreg_to_num()
62 return physreg; in ra_physreg_to_num()
Dir3_ra_validate.c223 physreg_t physreg = ra_reg_get_physreg(dst); in propagate_normal_instr() local
225 file->regs[physreg + i] = (struct reg_state){ in propagate_normal_instr()
443 physreg_t physreg = ra_reg_get_physreg(src); in check_reaching_src() local
451 struct reg_state actual = file->regs[physreg + i]; in check_reaching_src()
Dir3_spill.c574 physreg_t physreg = ra_reg_get_physreg(dst); in insert_dst() local
575 physreg_t max = physreg + reg_size(dst); in insert_dst()
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
Dscheduler.c1029 int physreg = ffsll(available) - 1; in try_spill_node() local
1031 ctx->live_physregs |= (1ull << physreg); in try_spill_node()
1034 store->index = physreg / 4; in try_spill_node()
1035 store->component = physreg % 4; in try_spill_node()
1052 &ctx->physreg_reads[physreg], reg_link) { in try_spill_node()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc43544 /* 94530*/ OPC_RecordChild2, // #2 = physreg input CPSR
43587 /* 94641*/ OPC_RecordChild2, // #2 = physreg input CPSR
43603 /* 94679*/ OPC_RecordChild2, // #2 = physreg input CPSR
43618 /* 94714*/ OPC_RecordChild2, // #2 = physreg input CPSR
43634 /* 94752*/ OPC_RecordChild2, // #2 = physreg input CPSR
43649 /* 94787*/ OPC_RecordChild2, // #2 = physreg input CPSR
43665 /* 94825*/ OPC_RecordChild2, // #2 = physreg input CPSR
43702 /* 94926*/ OPC_RecordChild2, // #2 = physreg input CPSR
43738 /* 95013*/ OPC_RecordChild2, // #2 = physreg input CPSR
43800 /* 95180*/ OPC_RecordChild2, // #2 = physreg input CPSR
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