| /third_party/optimized-routines/string/aarch64/ |
| D | strlen-sve.S | 20 ptrue p2.b /* all ones; loop invariant */
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| D | strcpy-sve.S | 28 ptrue p2.b, all /* all ones; loop invariant */
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| D | strcmp-sve.S | 21 ptrue p1.b, all /* all ones; loop invariant */
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| D | strchr-sve.S | 28 ptrue p1.b /* all ones; loop invariant */
|
| D | strrchr-sve.S | 21 ptrue p1.b /* all ones; loop invariant */
|
| /third_party/vixl/doc/aarch64/topics/ |
| D | state-trace.md | 136 0x00007f66e539b0bc 25d8e3a7 ptrue p7.d, all
|
| /third_party/vixl/test/aarch64/ |
| D | test-disasm-sve-aarch64.cc | 5901 COMPARE(ptrue(p0.VnB(), SVE_POW2), "ptrue p0.b, pow2"); in TEST()
5902 COMPARE(ptrue(p1.VnH(), SVE_VL1), "ptrue p1.h, vl1"); in TEST()
5903 COMPARE(ptrue(p2.VnS(), SVE_VL8), "ptrue p2.s, vl8"); in TEST()
5904 COMPARE(ptrue(p3.VnD(), SVE_VL16), "ptrue p3.d, vl16"); in TEST()
5905 COMPARE(ptrue(p4.VnB(), SVE_VL256), "ptrue p4.b, vl256"); in TEST()
5906 COMPARE(ptrue(p5.VnH(), SVE_MUL3), "ptrue p5.h, mul3"); in TEST()
5907 COMPARE(ptrue(p6.VnS(), SVE_MUL4), "ptrue p6.s, mul4"); in TEST()
5908 COMPARE(ptrue(p7.VnD(), SVE_ALL), "ptrue p7.d"); in TEST()
5920 COMPARE(ptrue(p7.VnS(), 0xd), "ptrue p7.s, vl256"); in TEST()
5921 COMPARE(ptrue(p8.VnD(), 0xe), "ptrue p8.d, #0xe"); in TEST()
[all …]
|
| D | test-assembler-sve-aarch64.cc | 3386 AssemblePtrueFn assemble = &MacroAssembler::ptrue; in PtrueHelper()
14799 const PRegisterM& ptrue, in FPSegmentPatternHelper() argument
14806 masm->Scvtf(ztmp, ptrue, ztmp); in FPSegmentPatternHelper()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12550 "m\004prfw\003psb\005pssbb\005ptest\005ptrue\006ptrues\007punpkhi\007pun"
16969 …{ 3715 /* ptrue */, AArch64::PTRUE_H, Convert__SVEPredicateHReg1_0__imm_95_31, AMFBS_HasSVE, { MCK…
16970 …{ 3715 /* ptrue */, AArch64::PTRUE_S, Convert__SVEPredicateSReg1_0__imm_95_31, AMFBS_HasSVE, { MCK…
16971 …{ 3715 /* ptrue */, AArch64::PTRUE_D, Convert__SVEPredicateDReg1_0__imm_95_31, AMFBS_HasSVE, { MCK…
16972 …{ 3715 /* ptrue */, AArch64::PTRUE_B, Convert__SVEPredicateBReg1_0__imm_95_31, AMFBS_HasSVE, { MCK…
16973 …{ 3715 /* ptrue */, AArch64::PTRUE_H, Convert__SVEPredicateHReg1_0__SVEPattern1_1, AMFBS_HasSVE, {…
16974 …{ 3715 /* ptrue */, AArch64::PTRUE_S, Convert__SVEPredicateSReg1_0__SVEPattern1_1, AMFBS_HasSVE, {…
16975 …{ 3715 /* ptrue */, AArch64::PTRUE_D, Convert__SVEPredicateDReg1_0__SVEPattern1_1, AMFBS_HasSVE, {…
16976 …{ 3715 /* ptrue */, AArch64::PTRUE_B, Convert__SVEPredicateBReg1_0__SVEPattern1_1, AMFBS_HasSVE, {…
24342 …{ 3715 /* ptrue */, AArch64::PTRUE_H, Convert__SVEPredicateHReg1_0__imm_95_31, AMFBS_HasSVE, { MCK…
[all …]
|
| D | AArch64GenAsmWriter.inc | 22599 /* 9467 */ "ptrue $\xFF\x01\x06\0"
22600 /* 9478 */ "ptrue $\xFF\x01\x10\0"
22601 /* 9489 */ "ptrue $\xFF\x01\x09\0"
22602 /* 9500 */ "ptrue $\xFF\x01\x0B\0"
|
| D | AArch64GenAsmWriter1.inc | 23320 /* 9445 */ "ptrue $\xFF\x01\x06\0"
23321 /* 9456 */ "ptrue $\xFF\x01\x10\0"
23322 /* 9467 */ "ptrue $\xFF\x01\x09\0"
23323 /* 9478 */ "ptrue $\xFF\x01\x0B\0"
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 113 def ptrue: PatFrag<(ops), (HexagonPTRUE)>;
115 def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>;
|
| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 6403 LogicPRegister Simulator::ptrue(VectorFormat vform, in ptrue() function in vixl::aarch64::Simulator
7630 ptrue(vform, ptemp, SVE_ALL); in match()
|
| D | simulator-aarch64.h | 4342 LogicPRegister ptrue(VectorFormat vform, LogicPRegister dst, int pattern);
|
| D | assembler-aarch64.h | 5218 void ptrue(const PRegisterWithLaneSize& pd, int pattern = SVE_ALL);
|
| D | macro-assembler-aarch64.h | 5674 ptrue(pd, pattern);
|
| D | assembler-sve-aarch64.cc | 6302 void Assembler::ptrue(const PRegisterWithLaneSize& pd, int pattern) { in ptrue() function in vixl::aarch64::Assembler
|
| D | simulator-aarch64.cc | 13539 ptrue(vform, pdn, instr->GetImmSVEPredicateConstraint()); in Simulator()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 299 defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
377 Instruction inst, Instruction ptrue>
379 (inst (IMPLICIT_DEF), (ptrue 31), $Op1)>;
|
| /third_party/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 9661 void ptrue(const PRegisterWithLaneSize& pd, int pattern = SVE_ALL)
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 692 "llvm.aarch64.sve.ptrue",
10825 23, // llvm.aarch64.sve.ptrue
|