Home
last modified time | relevance | path

Searched refs:r3 (Results 1 – 25 of 1478) sorted by relevance

12345678910>>...60

/third_party/mesa3d/src/util/
Du_math.c144 float *r0, *r1, *r2, *r3; in util_invert_mat4x4() local
154 r0 = wtmp[0], r1 = wtmp[1], r2 = wtmp[2], r3 = wtmp[3]; in util_invert_mat4x4()
165 r3[0] = MAT(m, 3, 0), r3[1] = MAT(m, 3, 1), r3[2] = MAT(m, 3, 2), r3[3] = MAT(m, 3, 3), in util_invert_mat4x4()
166 r3[7] = 1.0, r3[4] = r3[5] = r3[6] = 0.0; in util_invert_mat4x4()
169 if (fabsf(r3[0]) > fabsf(r2[0])) in util_invert_mat4x4()
170 SWAP_ROWS(r3, r2); in util_invert_mat4x4()
181 m3 = r3[0] / r0[0]; in util_invert_mat4x4()
185 r3[1] -= m3 * s; in util_invert_mat4x4()
189 r3[2] -= m3 * s; in util_invert_mat4x4()
193 r3[3] -= m3 * s; in util_invert_mat4x4()
[all …]
/third_party/openh264/codec/encoder/core/arm/
Dintra_pred_neon.S53 sub r3, r1, #1
54 GET_8BYTE_DATA d0, r3, r2
55 GET_8BYTE_DATA d1, r3, r2
58 sub r3, r1, r2
59 vldm r3, {d2, d3}
74 mov r3, #4
80 subs r3, #1
98 adr r3, CONST0_GET_I16X16_LUMA_PRED_PLANE
99 vldr d0, [r3]
102 sub r3, r1, r2
[all …]
/third_party/musl/src/string/arm/
Dmemcpy.S69 rsb r3, r1, #0
70 ands r3, r3, #3
77 movs r12, r3, lsl #31
78 sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
79 ldrbmi r3, [r1], #1
82 strbmi r3, [r0], #1
99 rsb r3, r0, #0
100 ands r3, r3, #0x1C
102 cmp r3, r2
103 andhi r3, r2, #0x1C
[all …]
/third_party/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc98 {{gt, r3, r1, r0}, true, gt, "gt r3 r1 r0", "gt_r3_r1_r0"},
99 {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
100 {{pl, r5, r3, r4}, true, pl, "pl r5 r3 r4", "pl_r5_r3_r4"},
102 {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"},
103 {{vc, r4, r3, r4}, true, vc, "vc r4 r3 r4", "vc_r4_r3_r4"},
105 {{ls, r3, r4, r0}, true, ls, "ls r3 r4 r0", "ls_r3_r4_r0"},
106 {{gt, r6, r4, r3}, true, gt, "gt r6 r4 r3", "gt_r6_r4_r3"},
113 {{lt, r4, r3, r3}, true, lt, "lt r4 r3 r3", "lt_r4_r3_r3"},
115 {{ls, r3, r3, r1}, true, ls, "ls r3 r3 r1", "ls_r3_r3_r1"},
118 {{eq, r4, r3, r0}, true, eq, "eq r4 r3 r0", "eq_r4_r3_r0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc98 {{eq, r0, r3, r0}, true, eq, "eq r0 r3 r0", "eq_r0_r3_r0"},
106 {{eq, r1, r3, r1}, true, eq, "eq r1 r3 r1", "eq_r1_r3_r1"},
114 {{eq, r2, r3, r2}, true, eq, "eq r2 r3 r2", "eq_r2_r3_r2"},
119 {{eq, r3, r0, r3}, true, eq, "eq r3 r0 r3", "eq_r3_r0_r3"},
120 {{eq, r3, r1, r3}, true, eq, "eq r3 r1 r3", "eq_r3_r1_r3"},
121 {{eq, r3, r2, r3}, true, eq, "eq r3 r2 r3", "eq_r3_r2_r3"},
122 {{eq, r3, r3, r3}, true, eq, "eq r3 r3 r3", "eq_r3_r3_r3"},
123 {{eq, r3, r4, r3}, true, eq, "eq r3 r4 r3", "eq_r3_r4_r3"},
124 {{eq, r3, r5, r3}, true, eq, "eq r3 r5 r3", "eq_r3_r5_r3"},
125 {{eq, r3, r6, r3}, true, eq, "eq r3 r6 r3", "eq_r3_r6_r3"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc105 {{{gt, r3, r3, r0}, true, gt, "gt r3 r3 r0", "gt_r3_r3_r0"},
112 {{hi, r6, r6, r3}, true, hi, "hi r6 r6 r3", "hi_r6_r6_r3"},
117 {{cc, r4, r4, r3}, true, cc, "cc r4 r4 r3", "cc_r4_r4_r3"},
118 {{mi, r5, r5, r3}, true, mi, "mi r5 r5 r3", "mi_r5_r5_r3"},
119 {{cs, r3, r3, r0}, true, cs, "cs r3 r3 r0", "cs_r3_r3_r0"},
122 {{cc, r3, r3, r6}, true, cc, "cc r3 r3 r6", "cc_r3_r3_r6"},
123 {{hi, r7, r7, r3}, true, hi, "hi r7 r7 r3", "hi_r7_r7_r3"},
126 {{le, r5, r5, r3}, true, le, "le r5 r5 r3", "le_r5_r5_r3"},
128 {{vs, r7, r7, r3}, true, vs, "vs r7 r7 r3", "vs_r7_r7_r3"},
129 {{cc, r0, r0, r3}, true, cc, "cc r0 r0 r3", "cc_r0_r0_r3"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc97 {{{mi, r3, r3, 90}, true, mi, "mi r3 r3 90", "mi_r3_r3_90"},
106 {{gt, r3, r3, 0}, true, gt, "gt r3 r3 0", "gt_r3_r3_0"},
113 {{lt, r3, r3, 207}, true, lt, "lt r3 r3 207", "lt_r3_r3_207"},
114 {{vs, r3, r3, 101}, true, vs, "vs r3 r3 101", "vs_r3_r3_101"},
121 {{hi, r3, r3, 62}, true, hi, "hi r3 r3 62", "hi_r3_r3_62"},
122 {{eq, r3, r3, 216}, true, eq, "eq r3 r3 216", "eq_r3_r3_216"},
135 {{ls, r3, r3, 114}, true, ls, "ls r3 r3 114", "ls_r3_r3_114"},
139 {{hi, r3, r3, 17}, true, hi, "hi r3 r3 17", "hi_r3_r3_17"},
141 {{hi, r3, r3, 20}, true, hi, "hi r3 r3 20", "hi_r3_r3_20"},
143 {{eq, r3, r3, 172}, true, eq, "eq r3 r3 172", "eq_r3_r3_172"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc865 {{al, r3, r3, 0}, false, al, "al r3 r3 0", "al_r3_r3_0"},
866 {{al, r3, r3, 1}, false, al, "al r3 r3 1", "al_r3_r3_1"},
867 {{al, r3, r3, 2}, false, al, "al r3 r3 2", "al_r3_r3_2"},
868 {{al, r3, r3, 3}, false, al, "al r3 r3 3", "al_r3_r3_3"},
869 {{al, r3, r3, 4}, false, al, "al r3 r3 4", "al_r3_r3_4"},
870 {{al, r3, r3, 5}, false, al, "al r3 r3 5", "al_r3_r3_5"},
871 {{al, r3, r3, 6}, false, al, "al r3 r3 6", "al_r3_r3_6"},
872 {{al, r3, r3, 7}, false, al, "al r3 r3 7", "al_r3_r3_7"},
873 {{al, r3, r3, 8}, false, al, "al r3 r3 8", "al_r3_r3_8"},
874 {{al, r3, r3, 9}, false, al, "al r3 r3 9", "al_r3_r3_9"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"},
105 {{le, r3, r3, ASR, r6}, true, le, "le r3 r3 ASR r6", "le_r3_r3_ASR_r6"},
107 {{pl, r3, r3, ASR, r2}, true, pl, "pl r3 r3 ASR r2", "pl_r3_r3_ASR_r2"},
113 {{ls, r6, r6, LSL, r3}, true, ls, "ls r6 r6 LSL r3", "ls_r6_r6_LSL_r3"},
122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"},
123 {{cs, r7, r7, ASR, r3}, true, cs, "cs r7 r7 ASR r3", "cs_r7_r7_ASR_r3"},
124 {{ne, r3, r3, ROR, r4}, true, ne, "ne r3 r3 ROR r4", "ne_r3_r3_ROR_r4"},
134 {{vc, r5, r5, ROR, r3}, true, vc, "vc r5 r5 ROR r3", "vc_r5_r5_ROR_r3"},
135 {{ls, r3, r3, LSL, r2}, true, ls, "ls r3 r3 LSL r2", "ls_r3_r3_LSL_r2"},
136 {{ls, r6, r6, ASR, r3}, true, ls, "ls r6 r6 ASR r3", "ls_r6_r6_ASR_r3"},
[all …]
Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc98 {{eq, r0, r3}, true, eq, "eq r0 r3", "eq_r0_r3"},
106 {{eq, r1, r3}, true, eq, "eq r1 r3", "eq_r1_r3"},
114 {{eq, r2, r3}, true, eq, "eq r2 r3", "eq_r2_r3"},
119 {{eq, r3, r0}, true, eq, "eq r3 r0", "eq_r3_r0"},
120 {{eq, r3, r1}, true, eq, "eq r3 r1", "eq_r3_r1"},
121 {{eq, r3, r2}, true, eq, "eq r3 r2", "eq_r3_r2"},
122 {{eq, r3, r3}, true, eq, "eq r3 r3", "eq_r3_r3"},
123 {{eq, r3, r4}, true, eq, "eq r3 r4", "eq_r3_r4"},
124 {{eq, r3, r5}, true, eq, "eq r3 r5", "eq_r3_r5"},
125 {{eq, r3, r6}, true, eq, "eq r3 r6", "eq_r3_r6"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc98 {{eq, r0, r3, 0}, true, eq, "eq r0 r3 0", "eq_r0_r3_0"},
106 {{eq, r1, r3, 0}, true, eq, "eq r1 r3 0", "eq_r1_r3_0"},
114 {{eq, r2, r3, 0}, true, eq, "eq r2 r3 0", "eq_r2_r3_0"},
119 {{eq, r3, r0, 0}, true, eq, "eq r3 r0 0", "eq_r3_r0_0"},
120 {{eq, r3, r1, 0}, true, eq, "eq r3 r1 0", "eq_r3_r1_0"},
121 {{eq, r3, r2, 0}, true, eq, "eq r3 r2 0", "eq_r3_r2_0"},
122 {{eq, r3, r3, 0}, true, eq, "eq r3 r3 0", "eq_r3_r3_0"},
123 {{eq, r3, r4, 0}, true, eq, "eq r3 r4 0", "eq_r3_r4_0"},
124 {{eq, r3, r5, 0}, true, eq, "eq r3 r5 0", "eq_r3_r5_0"},
125 {{eq, r3, r6, 0}, true, eq, "eq r3 r6 0", "eq_r3_r6_0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc104 {{eq, r3, r4, 5}, true, eq, "eq r3 r4 5", "eq_r3_r4_5"},
113 {{eq, r3, r4, 4}, true, eq, "eq r3 r4 4", "eq_r3_r4_4"},
117 {{hi, r3, r1, 0}, true, hi, "hi r3 r1 0", "hi_r3_r1_0"},
122 {{ls, r6, r3, 0}, true, ls, "ls r6 r3 0", "ls_r6_r3_0"},
124 {{le, r5, r3, 2}, true, le, "le r5 r3 2", "le_r5_r3_2"},
131 {{ls, r3, r0, 3}, true, ls, "ls r3 r0 3", "ls_r3_r0_3"},
134 {{cs, r3, r1, 7}, true, cs, "cs r3 r1 7", "cs_r3_r1_7"},
139 {{gt, r0, r3, 5}, true, gt, "gt r0 r3 5", "gt_r0_r3_5"},
142 {{ne, r6, r3, 0}, true, ne, "ne r6 r3 0", "ne_r6_r3_0"},
145 {{le, r3, r0, 6}, true, le, "le r3 r0 6", "le_r3_r0_6"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc121 {{al, r0, r3, 0}, false, al, "al r0 r3 0", "al_r0_r3_0"},
122 {{al, r0, r3, 1}, false, al, "al r0 r3 1", "al_r0_r3_1"},
123 {{al, r0, r3, 2}, false, al, "al r0 r3 2", "al_r0_r3_2"},
124 {{al, r0, r3, 3}, false, al, "al r0 r3 3", "al_r0_r3_3"},
125 {{al, r0, r3, 4}, false, al, "al r0 r3 4", "al_r0_r3_4"},
126 {{al, r0, r3, 5}, false, al, "al r0 r3 5", "al_r0_r3_5"},
127 {{al, r0, r3, 6}, false, al, "al r0 r3 6", "al_r0_r3_6"},
128 {{al, r0, r3, 7}, false, al, "al r0 r3 7", "al_r0_r3_7"},
185 {{al, r1, r3, 0}, false, al, "al r1 r3 0", "al_r1_r3_0"},
186 {{al, r1, r3, 1}, false, al, "al r1 r3 1", "al_r1_r3_1"},
[all …]
Dtest-assembler-rd-rn-rm-t32.cc102 {{r3, r1, r0}, false, al, "r3 r1 r0", "r3_r1_r0"},
104 {{r3, r14, r11}, false, al, "r3 r14 r11", "r3_r14_r11"},
105 {{r12, r3, r1}, false, al, "r12 r3 r1", "r12_r3_r1"},
106 {{r3, r9, r2}, false, al, "r3 r9 r2", "r3_r9_r2"},
107 {{r1, r3, r3}, false, al, "r1 r3 r3", "r1_r3_r3"},
111 {{r3, r8, r8}, false, al, "r3 r8 r8", "r3_r8_r8"},
114 {{r10, r14, r3}, false, al, "r10 r14 r3", "r10_r14_r3"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
129 {{r3, r0, r1}, false, al, "r3 r0 r1", "r3_r0_r1"},
131 {{r14, r5, r3}, false, al, "r14 r5 r3", "r14_r5_r3"},
[all …]
Dtest-assembler-rd-rn-rm-a32.cc102 {{r3, r1, r0}, false, al, "r3 r1 r0", "r3_r1_r0"},
104 {{r3, r14, r11}, false, al, "r3 r14 r11", "r3_r14_r11"},
105 {{r12, r3, r1}, false, al, "r12 r3 r1", "r12_r3_r1"},
106 {{r3, r9, r2}, false, al, "r3 r9 r2", "r3_r9_r2"},
107 {{r1, r3, r3}, false, al, "r1 r3 r3", "r1_r3_r3"},
111 {{r3, r8, r8}, false, al, "r3 r8 r8", "r3_r8_r8"},
114 {{r10, r14, r3}, false, al, "r10 r14 r3", "r10_r14_r3"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
129 {{r3, r0, r1}, false, al, "r3 r0 r1", "r3_r0_r1"},
131 {{r14, r5, r3}, false, al, "r14 r5 r3", "r14_r5_r3"},
[all …]
/third_party/vixl/benchmarks/aarch32/
Dasm-disasm-speed-test.cc206 __ movs(Narrow, r3, 0U); in Generate_1()
220 __ strb(Narrow, r3, MemOperand(r4, 24)); in Generate_1()
221 __ str(Narrow, r3, MemOperand(r4, 28)); in Generate_1()
222 __ strb(r3, MemOperand(r4, 32)); in Generate_1()
223 __ strb(r3, MemOperand(r4, 36)); in Generate_1()
224 __ str(Narrow, r3, MemOperand(r4, 52)); in Generate_1()
225 __ str(Narrow, r3, MemOperand(r4, 56)); in Generate_1()
226 __ str(Narrow, r3, MemOperand(r4, 60)); in Generate_1()
227 __ str(Narrow, r3, MemOperand(r4, 68)); in Generate_1()
228 __ str(Narrow, r3, MemOperand(r4, 72)); in Generate_1()
[all …]
/third_party/node/deps/v8/src/regexp/ppc/
Dregexp-macro-assembler-ppc.cc122 __ li(r3, Operand(FAILURE)); in RegExpMacroAssemblerPPC()
163 __ LoadU64(r3, register_location(reg), r0); in AdvanceRegister()
165 __ add(r3, r3, r0); in AdvanceRegister()
166 __ StoreU64(r3, register_location(reg), r0); in AdvanceRegister()
175 __ LoadU64(r3, MemOperand(frame_pointer(), kBacktrackCount), r0); in Backtrack()
176 __ addi(r3, r3, Operand(1)); in Backtrack()
177 __ StoreU64(r3, MemOperand(frame_pointer(), kBacktrackCount), r0); in Backtrack()
179 __ CmpS64(r3, r0); in Backtrack()
193 Pop(r3); in Backtrack()
194 __ add(r3, r3, code_pointer()); in Backtrack()
[all …]
/third_party/typescript/tests/baselines/reference/
DanyAssignabilityInInheritance.js13 var r3 = foo2(a); // any, not a subtype of number so it skips that overload, is a subtype of itself…
17 var r3 = foo3(a); // any
21 var r3 = foo3(a); // any
25 var r3 = foo3(a); // any
29 var r3 = foo3(a); // any
33 var r3 = foo3(a); // any
37 var r3 = foo3(a); // any
42 var r3 = foo3(a); // any
47 var r3 = foo3(a); // any
52 var r3 = foo3(a); // any
[all …]
DobjectTypeWithStringNamedNumericProperty.js20 var r3 = c['1']; variable
21 var r3 = c[1];
23 var r3 = c[1.]; // same as indexing by 1 when done numerically
26 var r3 = c[1.0]; // same as indexing by 1 when done numerically
51 var r3 = i['1'];
52 var r3 = c[1];
54 var r3 = c[1.]; // same as indexing by 1 when done numerically
57 var r3 = c[1.0]; // same as indexing by 1 when done numerically
81 var r3 = a['1'];
82 var r3 = c[1];
[all …]
/third_party/musl/porting/uniproton/kernel/src/string/arch/arm/
Dmemcpy_le.S74 rsb r3, r1, #0
75 ands r3, r3, #3
82 movs r12, r3, lsl #31
83 sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
85 ldrbmi r3, [r1], #1
86 strbmi r3, [r0], #1
106 rsb r3, r0, #0
107 ands r3, r3, #0x1C
109 cmp r3, r2
111 andhi r3, r2, #0x1C
[all …]
/third_party/musl/porting/liteos_m/kernel/src/string/arch/arm/
Dmemcpy_le.S78 rsb r3, r1, #0
79 ands r3, r3, #3
86 movs r12, r3, lsl #31
87 sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
89 ldrbmi r3, [r1], #1
90 strbmi r3, [r0], #1
110 rsb r3, r0, #0
111 ands r3, r3, #0x1C
113 cmp r3, r2
115 andhi r3, r2, #0x1C
[all …]
/third_party/ffmpeg/libavcodec/arm/
Dsbcdsp_armv6.S36 push {r1, r3-r7, lr}
43 smlad r3, r4, r6, r14
47 smlad r3, r8, r10, r3
51 smlad r3, r4, r6, r3
55 smlad r3, r8, r10, r3
59 smlad r3, r4, r6, r3 @ t1[0] is done
63 pkhtb r3, r12, r3, asr #16 @ combine t1[0] and t1[1]
85 smuad r4, r3, r4
86 smuad r5, r3, r5
89 smuad r6, r3, r6
[all …]
/third_party/musl/src/fenv/arm/
Dfenv-hf.S17 fmrx r3, fpscr
18 bic r3, r3, #0xc00000
19 orr r3, r3, r0
20 fmxr fpscr, r3
28 fmrx r3, fpscr
29 and r0, r0, r3
36 fmrx r3, fpscr
37 bic r3, r3, r0
38 fmxr fpscr, r3
46 fmrx r3, fpscr
[all …]
/third_party/libffi/src/powerpc/
Ddarwin_closure.S149 sg r3, (PARENT_PARM_BASE )(r1)
175 mr r3,r11
191 sg r3,LINKAGE_SIZE(r1) ; ffi_type * result_type
192 lg r0,0(r3) ; size => r0
193 lhz r3,FFI_TYPE_TYPE(r3) ; type => r3
204 slwi r3,r3,4 /* Now multiply return type by 16. */
205 add r3,r3,r4 /* Add contents of table to table address. */
206 mtctr r3
230 lg r3,0(r5)
259 lbz r3,7(r5)
[all …]
/third_party/node/deps/openssl/config/archs/linux-armv4/asm/crypto/sha/
Dsha1-armv4-large.S21 adr r3,.Lsha1_block
22 ldr r12,[r3,r12] @ OPENSSL_armcap_P
34 ldmia r0,{r3,r4,r5,r6,r7}
52 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
58 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
88 and r10,r3,r10,ror#2
100 eor r10,r3,r4 @ F_xx_xx
107 eor r10,r3,r4 @ F_xx_xx
125 eor r10,r7,r3 @ F_xx_xx
132 eor r10,r7,r3 @ F_xx_xx
[all …]

12345678910>>...60