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Searched refs:radeon_set_uconfig_reg (Results 1 – 17 of 17) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_spm.c81 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, block_sel->grbm_gfx_index); in radv_emit_spm_counters()
98 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in radv_emit_spm_counters()
116 radeon_set_uconfig_reg(cs, R_037200_RLC_SPM_PERFMON_CNTL, in radv_emit_spm_setup()
119 radeon_set_uconfig_reg(cs, R_037204_RLC_SPM_PERFMON_RING_BASE_LO, va); in radv_emit_spm_setup()
120 radeon_set_uconfig_reg(cs, R_037208_RLC_SPM_PERFMON_RING_BASE_HI, in radv_emit_spm_setup()
122 radeon_set_uconfig_reg(cs, R_03720C_RLC_SPM_PERFMON_RING_SIZE, ring_size); in radv_emit_spm_setup()
130 radeon_set_uconfig_reg(cs, R_03726C_RLC_SPM_ACCUM_MODE, 0); in radv_emit_spm_setup()
131 radeon_set_uconfig_reg(cs, R_037210_RLC_SPM_PERFMON_SEGMENT_SIZE, 0); in radv_emit_spm_setup()
132 radeon_set_uconfig_reg(cs, R_03727C_RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE, in radv_emit_spm_setup()
137 radeon_set_uconfig_reg(cs, R_037280_RLC_SPM_PERFMON_GLB_SEGMENT_SIZE, in radv_emit_spm_setup()
[all …]
Dradv_sqtt.c96 radeon_set_uconfig_reg( in radv_emit_thread_trace_start()
138 radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2, in radv_emit_thread_trace_start()
141 radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va); in radv_emit_thread_trace_start()
143 radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, S_030CC4_SIZE(shifted_size)); in radv_emit_thread_trace_start()
145 radeon_set_uconfig_reg(cs, R_030CD4_SQ_THREAD_TRACE_CTRL, S_030CD4_RESET_BUFFER(1)); in radv_emit_thread_trace_start()
156 radeon_set_uconfig_reg(cs, R_030CC8_SQ_THREAD_TRACE_MASK, thread_trace_mask); in radv_emit_thread_trace_start()
159 radeon_set_uconfig_reg( in radv_emit_thread_trace_start()
164 radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK, in radv_emit_thread_trace_start()
167 radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff); in radv_emit_thread_trace_start()
169 radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER, S_030CEC_HIWATER(4)); in radv_emit_thread_trace_start()
[all …]
Dsi_cmd_buffer.c54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
110 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY, in si_emit_compute()
287 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0); in si_emit_graphics()
288 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0); in si_emit_graphics()
289 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0); in si_emit_graphics()
290 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0); in si_emit_graphics()
291 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0); in si_emit_graphics()
299 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0); in si_emit_graphics()
300 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0); in si_emit_graphics()
[all …]
Dradv_perfcounter.c56 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_perfcounter_emit_spm_reset()
65 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_perfcounter_emit_spm_start()
78 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_perfcounter_emit_spm_stop()
484 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value); in radv_emit_instance()
593 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_pc_stop_and_sample()
674 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_pc_begin_query()
719 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_pc_begin_query()
753 radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL, in radv_pc_end_query()
Dradv_cs.h163 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg() function
Dradv_device.c4129 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size)); in radv_emit_tess_factor_ring()
4130 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8); in radv_emit_tess_factor_ring()
4133 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI, in radv_emit_tess_factor_ring()
4136 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(tf_va >> 40)); in radv_emit_tess_factor_ring()
4139 …radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, device->physical_device->hs.hs_offchip_p… in radv_emit_tess_factor_ring()
Dradv_pipeline.c2428 radeon_set_uconfig_reg( in gfx10_emit_ge_pc_alloc()
5892 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl); in radv_pipeline_emit_hw_ngg()
6578 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, in gfx10_pipeline_emit_ge_cntl()
6593 radeon_set_uconfig_reg(ctx_cs, R_030998_VGT_GS_OUT_PRIM_TYPE, vgt_gs_out_prim_type); in radv_pipeline_emit_vgt_gs_out()
Dradv_cmd_buffer.c1904 radeon_set_uconfig_reg(cmd_buffer->cs, R_03098C_GE_VRS_RATE, in radv_emit_fragment_shading_rate()
1932 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_GE_MULTI_PRIM_IB_RESET_EN, in radv_emit_primitive_restart_enable()
1935 radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, in radv_emit_primitive_restart_enable()
10045 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0); in radv_flush_vgt_streamout()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_perfcounter.c84 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, value); in si_pc_emit_instance()
133 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, in si_pc_emit_start()
137 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, in si_pc_emit_start()
161 radeon_set_uconfig_reg( in si_pc_emit_stop()
175 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, in si_pc_emit_spm_start()
200 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, in si_pc_emit_spm_stop()
212 radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, in si_pc_emit_spm_reset()
285 radeon_set_uconfig_reg(R_037390_RLC_PERFMON_CLK_CNTL, in si_inhibit_clockgating()
288 radeon_set_uconfig_reg(R_0372FC_RLC_PERFMON_CLK_CNTL, in si_inhibit_clockgating()
767 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, block_sel->grbm_gfx_index); in si_emit_spm_counters()
[all …]
Dsi_sqtt.c98 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, in si_emit_thread_trace_start()
146 radeon_set_uconfig_reg(R_030CDC_SQ_THREAD_TRACE_BASE2, in si_emit_thread_trace_start()
149 radeon_set_uconfig_reg(R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va); in si_emit_thread_trace_start()
151 radeon_set_uconfig_reg(R_030CC4_SQ_THREAD_TRACE_SIZE, in si_emit_thread_trace_start()
154 radeon_set_uconfig_reg(R_030CD4_SQ_THREAD_TRACE_CTRL, in si_emit_thread_trace_start()
165 radeon_set_uconfig_reg(R_030CC8_SQ_THREAD_TRACE_MASK, in si_emit_thread_trace_start()
169 radeon_set_uconfig_reg(R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK, in si_emit_thread_trace_start()
175 radeon_set_uconfig_reg(R_030CD0_SQ_THREAD_TRACE_PERF_MASK, in si_emit_thread_trace_start()
179 radeon_set_uconfig_reg(R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff); in si_emit_thread_trace_start()
181 radeon_set_uconfig_reg(R_030CEC_SQ_THREAD_TRACE_HIWATER, in si_emit_thread_trace_start()
[all …]
Dsi_build_pm4.h144 #define radeon_set_uconfig_reg(reg, value) do { \ macro
279 radeon_set_uconfig_reg(offset, __value); \
Dsi_state_streamout.c232 radeon_set_uconfig_reg(reg_strmout_cntl, 0); in si_flush_vgt_streamout()
Dsi_state_draw.cpp1175 radeon_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); in si_emit_rasterizer_prim_state()
1362 radeon_set_uconfig_reg(R_03096C_GE_CNTL, ge_cntl); in gfx10_emit_ge_cntl()
1394 radeon_set_uconfig_reg(R_030908_VGT_PRIMITIVE_TYPE, vgt_prim); in si_emit_draw_registers()
1406 radeon_set_uconfig_reg(R_03092C_GE_MULTI_PRIM_IB_RESET_EN, primitive_restart); in si_emit_draw_registers()
1408 radeon_set_uconfig_reg(R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart); in si_emit_draw_registers()
Dsi_state_shaders.cpp3859 radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE, in si_update_gs_ring_buffers()
3863 radeon_set_uconfig_reg(R_030904_VGT_GSVS_RING_SIZE, in si_update_gs_ring_buffers()
4129 radeon_set_uconfig_reg(R_030938_VGT_TF_RING_SIZE, in si_init_tess_factor_ring()
4131 radeon_set_uconfig_reg(R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8); in si_init_tess_factor_ring()
4133 radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI, in si_init_tess_factor_ring()
4136 radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, in si_init_tess_factor_ring()
4139 radeon_set_uconfig_reg(R_03093C_VGT_HS_OFFCHIP_PARAM, in si_init_tess_factor_ring()
Dsi_compute.c428 radeon_set_uconfig_reg(R_0301EC_CP_COHER_START_DELAY, in si_emit_initial_compute_regs()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h189 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg() function
/third_party/mesa3d/docs/relnotes/
D21.3.0.rst2707 - radeonsi: remove the unused cs parameter from radeon_set_uconfig_reg