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Searched refs:reg3 (Results 1 – 25 of 47) sorted by relevance

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/third_party/node/deps/openssl/openssl/crypto/aria/
Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
492 reg3 = GET_U32_BE(in, 3); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
526 reg3 = rk->u[3] ^ MAKE_U32( in ossl_aria_encrypt()
[all …]
/third_party/openssl/crypto/aria/
Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
492 reg3 = GET_U32_BE(in, 3); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
526 reg3 = rk->u[3] ^ MAKE_U32( in ossl_aria_encrypt()
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/third_party/elfutils/tests/
Drun-dwarfcfi.sh41 reg3: same_value
58 reg3: undefined
75 reg3: undefined
92 reg3: undefined
109 reg3: undefined
126 reg3: undefined
Drun-varlocs.sh68 [40051c,40052a) {reg3}
107 [400408,400421) {reg3}
179 [40118e,40119c) {reg3}
181 [4011a7,4011b5) {reg3}
257 [40118e,40119c) {reg3}
259 [4011a7,4011b5) {reg3}
331 [40050e,40051c) {reg3}
333 [400527,400535) {reg3}
Drun-readelf-zdebug-rel.sh237 [ 0] reg3
243 [ 0] reg3
246 [ 0] reg3
Drun-addrcfi.sh36 integer reg3 (%ebx): same_value
83 integer reg3 (%ebx): same_value
135 integer reg3 (%rbx): undefined
201 integer reg3 (%rbx): undefined
305 integer reg3 (r3): undefined
1327 integer reg3 (r3): undefined
2355 integer reg3 (r3): undefined
3381 integer reg3 (%r3): undefined
3458 integer reg3 (%r3): undefined
3536 integer reg3 (r3): undefined
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/third_party/vixl/src/aarch64/
Dregisters-aarch64.h972 const CPURegister& reg3 = NoReg,
986 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1028 const CPURegister& reg3 = NoCPUReg,
1037 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
1052 const CPURegister& reg3 = NoReg,
1061 even &= !reg3.IsValid() || ((reg3.GetCode() % 2) == 0);
1077 const CPURegister& reg3 = NoCPUReg,
1088 if (!reg3.IsValid()) {
1090 } else if (reg3.GetCode() !=
1098 ((reg3.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
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Dmacro-assembler-aarch64.cc3037 const Register& reg3, in Emit() argument
3041 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3051 const VRegister& reg3, in Emit() argument
3054 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3061 const CPURegister& reg3, in Emit() argument
3067 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Emit()
3101 const Register& reg3, in Emit() argument
3104 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3111 const VRegister& reg3, in Emit() argument
3114 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
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Doperands-aarch64.h44 CPURegister reg3 = NoCPUReg,
46 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
49 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
/third_party/node/deps/v8/src/interpreter/
Dbytecode-register.cc105 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous() argument
110 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) { in AreContiguous()
113 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
Dbytecode-register.h86 Register reg3 = invalid_value(),
/third_party/ffmpeg/libavcodec/mips/
Dvp9_idct_msa.c968 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
1008 VP9_DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1); in vp9_idct16_1d_columns_addblk_msa()
1009 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vp9_idct16_1d_columns_addblk_msa()
1011 loc1 = reg15 + reg3; in vp9_idct16_1d_columns_addblk_msa()
1012 reg3 = reg15 - reg3; in vp9_idct16_1d_columns_addblk_msa()
1045 VP9_DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13); in vp9_idct16_1d_columns_addblk_msa()
1046 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vp9_idct16_1d_columns_addblk_msa()
1052 reg3 = tmp7; in vp9_idct16_1d_columns_addblk_msa()
1060 SRARI_H4_SH(reg3, reg13, reg11, reg5, 6); in vp9_idct16_1d_columns_addblk_msa()
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Dh264pred_msa.c217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
268 reg3 = reg2 + vec6; in intra_predict_plane_16x16_msa()
271 SRA_4V(reg0, reg1, reg2, reg3, 5); in intra_predict_plane_16x16_msa()
273 PCKEV_H2_SH(reg1, reg0, reg3, reg2, vec11, vec12); in intra_predict_plane_16x16_msa()
/third_party/ffmpeg/libavcodec/aarch64/
Dvp9mc_16bpp_neon.S326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
329 sqrshrun \reg3\().4h, \reg3\().4s, #7
339 umin \reg3\().4h, \reg3\().4h, \minreg\().4h
344 urhadd \reg3\().4h, \reg3\().4h, \tmp3\().4h
349 st1 {\reg3\().4h}, [x0], x1
355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
358 sqrshrun \reg2\().4h, \reg3\().4s, #7
360 sqrshrun \reg3\().4h, \reg5\().4s, #7
361 sqrshrun2 \reg3\().8h, \reg6\().4s, #7
372 umin \reg3\().8h, \reg3\().8h, \minreg\().8h
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Dvp9mc_neon.S407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
410 sqrshrun \reg3\().8b, \reg3\().8h, #7
419 urhadd \reg3\().8b, \reg3\().8b, \tmp3\().8b
424 st1 {\reg3\().8b}, [x0], x1
/third_party/mesa3d/src/panfrost/bifrost/
Ddisassemble.c152 else if (regs.reg2 == regs.reg3) in DecodeRegCtrl()
183 fprintf(fp, "slot 3: r%u (write %s) ", srcs.reg3, slot3_fma); in dump_regs()
185 fprintf(fp, "slot 3: r%u (write lo %s) ", srcs.reg3, slot3_fma); in dump_regs()
187 fprintf(fp, "slot 3: r%u (write hi %s) ", srcs.reg3, slot3_fma); in dump_regs()
213 fprintf(fp, "r%u:t0", next_regs->reg3); in bi_disasm_dest_fma()
226 fprintf(fp, "r%u:t1", next_regs->reg3); in bi_disasm_dest_add()
Dbifrost.h228 unsigned reg3 : 6; member
Dbi_pack.c268 s.reg3 = regs.slot[3]; in bi_pack_registers()
/third_party/musl/src/thread/powerpc/
D__set_thread_area.s6 # mov pointer in reg3 into r2
/third_party/vixl/src/aarch32/
Dinstructions-aarch32.h465 constexpr RegisterList(Register reg1, Register reg2, Register reg3)
467 RegisterToList(reg3)) {}
468 constexpr RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
470 RegisterToList(reg3) | RegisterToList(reg4)) {}
556 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList() argument
558 RegisterToList(reg3)) {} in VRegisterList()
559 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList() argument
561 RegisterToList(reg3) | RegisterToList(reg4)) {} in VRegisterList()
Dmacro-assembler-aarch32.cc453 CPURegister reg3, in Printf() argument
463 PushRegister(reg3); in Printf()
476 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) | in Printf()
481 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() + in Printf()
502 if (reg3.GetType() == CPURegister::kRRegister) { in Printf()
503 available_registers.Remove(Register(reg3.GetCode())); in Printf()
517 PushRegister(reg3); in Printf()
528 PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type); in Printf()
/third_party/node/deps/v8/src/codegen/arm64/
Dregister-arm64.h515 const CPURegister& reg3 = NoReg, const CPURegister& reg4 = NoReg,
525 const CPURegister& reg3 = NoCPUReg, const CPURegister& reg4 = NoCPUReg,
533 const VRegister& reg3 = NoVReg,
542 const VRegister& reg3 = NoVReg,
Dassembler-arm64.cc225 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
234 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
261 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
267 match &= !reg3.is_valid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
277 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat() argument
280 (!reg3.is_valid() || reg3.IsSameFormat(reg1)) && in AreSameFormat()
285 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive() argument
288 DCHECK(!reg3.is_valid() && !reg4.is_valid()); in AreConsecutive()
294 if (!reg3.is_valid()) { in AreConsecutive()
297 } else if (reg3.code() != ((reg2.code() + 1) % kNumberOfVRegisters)) { in AreConsecutive()
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/third_party/ffmpeg/libavcodec/x86/
Dhevc_mc.asm482 %define %%reg3 %8
487 %define %%reg3 m3
507 pmaddubsw %%reg3, %4
508 paddw %%reg1, %%reg3
516 pmaddwd %%reg3, %4
517 paddd %%reg1, %%reg3
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFMA.td172 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
174 // FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2;

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