Searched refs:regclasses (Results 1 – 14 of 14) sorted by relevance
466 RegClass* regclasses = ctx->program->temp_rc.data() + ctx->first_temp_id; in init_context() local579 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr) in init_context()587 regclasses[alu_instr->dest.dest.ssa.index] = rc; in init_context()594 regclasses[nir_instr_as_load_const(instr)->def.index] = rc; in init_context()740 if (regclasses[intrinsic->src[i].ssa->index].type() == RegType::vgpr) in init_context()747 regclasses[intrinsic->dest.ssa.index] = rc; in init_context()760 regclasses[tex->dest.ssa.index] = rc; in init_context()765 regclasses[entry->dest.ssa.index] = regclasses[entry->src.ssa->index]; in init_context()773 regclasses[nir_instr_as_ssa_undef(instr)->def.index] = rc; in init_context()787 if (regclasses[src->src.ssa->index].type() == RegType::vgpr) in init_context()[all …]
59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()360 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()364 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
1767 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()2073 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
4197 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
197 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()226 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
172 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
33 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
224 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
526 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
661 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
581 // FIXME: This could be better modeled by looking at the regclasses of the operands.
1196 - aco: add sub-dword regclasses1240 - aco: setup subdword regclasses for ssa_undef & load_const
4042 - aco: keep track of temporaries' regclasses in the Program
5182 - aco: ensure that definitions fixed to operands have matching regclasses