/third_party/astc-encoder/Source/ |
D | astcenc_mathlib_softfloat.cpp | 109 static uint32_t rtne_shift32(uint32_t inp, uint32_t shamt) in rtne_shift32() argument 111 uint32_t vl1 = UINT32_C(1) << shamt; in rtne_shift32() 116 inp2 >>= shamt; in rtne_shift32() 120 static uint32_t rtna_shift32(uint32_t inp, uint32_t shamt) in rtna_shift32() argument 122 uint32_t vl1 = (UINT32_C(1) << shamt) >> 1; in rtna_shift32() 124 inp >>= shamt; in rtna_shift32() 128 static uint32_t rtup_shift32(uint32_t inp, uint32_t shamt) in rtup_shift32() argument 130 uint32_t vl1 = UINT32_C(1) << shamt; in rtup_shift32() 133 inp >>= shamt; in rtup_shift32()
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D | astcenc_color_unquantize.cpp | 472 int shamt = shamts[mode]; in hdr_rgbo_unpack() local 473 red <<= shamt; in hdr_rgbo_unpack() 474 green <<= shamt; in hdr_rgbo_unpack() 475 blue <<= shamt; in hdr_rgbo_unpack() 476 scale <<= shamt; in hdr_rgbo_unpack()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfo.td | 112 // TODO: should ensure invalid shamt is rejected when decoding. 330 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr, 331 "$rd, $rs1, $shamt">, 353 (ins GPR:$rs1, uimm5:$shamt), opcodestr, 354 "$rd, $rs1, $shamt">, 713 def : InstAlias<"sll $rd, $rs1, $shamt", 714 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 715 def : InstAlias<"srl $rd, $rs1, $shamt", 716 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>; 717 def : InstAlias<"sra $rd, $rs1, $shamt", [all …]
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D | RISCVInstrFormats.td | 229 bits<6> shamt; 236 let Inst{25-20} = shamt; 246 bits<5> shamt; 253 let Inst{24-20} = shamt;
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D | RISCVInstrInfoC.td | 27 // TODO: should ensure invalid shamt is rejected when decoding.
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86InstrShiftRotate.td | 847 (ins GR32:$src1, u8imm:$shamt), "", 848 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>; 850 (ins GR64:$src1, u8imm:$shamt), "", 851 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>; 854 (ins GR32:$src1, u8imm:$shamt), "", 855 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>; 857 (ins GR64:$src1, u8imm:$shamt), "", 858 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>; 862 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer. 867 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer. [all …]
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/third_party/skia/third_party/externals/swiftshader/third_party/astc-encoder/Source/ |
D | astc_color_unquantize.cpp | 443 int shamt = shamts[mode]; in hdr_rgbo_unpack3() local 444 red <<= shamt; in hdr_rgbo_unpack3() 445 green <<= shamt; in hdr_rgbo_unpack3() 446 blue <<= shamt; in hdr_rgbo_unpack3() 447 scale <<= shamt; in hdr_rgbo_unpack3()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsInstrFormats.td | 18 // shamt - only used on shift instructions, contains the shift amount. 148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 158 bits<5> shamt; 167 let Inst{10-6} = shamt; 280 bits<5> shamt; 289 let Inst{10-6} = shamt;
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D | MicroMipsInstrFormats.td | 98 bits<3> shamt; 105 let Inst{3-1} = shamt; 364 bits<5> shamt; 371 let Inst{15-11} = shamt;
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D | MicroMipsInstrInfo.td | 332 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 333 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>; 797 (rotr GPR32Opnd:$rt, immZExt5:$shamt))]; 1384 def : MipsInstAlias<"sll $rd, $shamt", 1385 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; 1386 def : MipsInstAlias<"sra $rd, $shamt", 1387 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; 1388 def : MipsInstAlias<"srl $rd, $shamt", 1389 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
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D | MicroMips32r6InstrFormats.td | 530 bits<5> shamt; 537 let Inst{15-11} = shamt;
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D | Mips64InstrInfo.td | 17 // shamt must fit in 6 bits. 414 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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D | MipsDSPInstrInfo.td | 1381 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
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D | MipsInstrInfo.td | 1247 // shamt field must fit in 5 bits. 1359 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), 1360 !strconcat(opstr, "\t$rd, $rt, $shamt"), 1361 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
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D | Mips16InstrInfo.td | 498 bits<5> shamt = 0;
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/third_party/node/deps/v8/src/codegen/riscv64/ |
D | assembler-riscv64.cc | 938 Register rd, Register rs1, uint8_t shamt) { in GenInstrIShift() argument 940 is_uint6(shamt)); in GenInstrIShift() 942 (rs1.code() << kRs1Shift) | (shamt << kShamtShift) | in GenInstrIShift() 948 Register rd, Register rs1, uint8_t shamt) { in GenInstrIShiftW() argument 950 is_uint5(shamt)); in GenInstrIShiftW() 952 (rs1.code() << kRs1Shift) | (shamt << kShamtWShift) | in GenInstrIShiftW() 1306 Register rs1, uint8_t shamt) { in GenInstrShift_ri() argument 1307 DCHECK(is_uint6(shamt)); in GenInstrShift_ri() 1308 GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt); in GenInstrShift_ri() 1327 Register rs1, uint8_t shamt) { in GenInstrShiftW_ri() argument [all …]
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D | assembler-riscv64.h | 437 void slli(Register rd, Register rs1, uint8_t shamt); 438 void srli(Register rd, Register rs1, uint8_t shamt); 439 void srai(Register rd, Register rs1, uint8_t shamt); 479 void slliw(Register rd, Register rs1, uint8_t shamt); 480 void srliw(Register rd, Register rs1, uint8_t shamt); 481 void sraiw(Register rd, Register rs1, uint8_t shamt); 1577 Register rd, Register rs1, uint8_t shamt); 1579 Register rd, Register rs1, uint8_t shamt); 1621 Register rs1, uint8_t shamt); 1629 Register rs1, uint8_t shamt);
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D | macro-assembler-riscv64.cc | 882 uint8_t shamt = static_cast<uint8_t>(rt.immediate()); in Sll32() local 883 slliw(rd, rs, shamt); in Sll32() 891 uint8_t shamt = static_cast<uint8_t>(rt.immediate()); in Sra32() local 892 sraiw(rd, rs, shamt); in Sra32() 900 uint8_t shamt = static_cast<uint8_t>(rt.immediate()); in Srl32() local 901 srliw(rd, rs, shamt); in Srl32() 910 uint8_t shamt = static_cast<uint8_t>(rt.immediate()); in Sra64() local 911 c_srai(rd, shamt); in Sra64() 913 uint8_t shamt = static_cast<uint8_t>(rt.immediate()); in Sra64() local 914 srai(rd, rs, shamt); in Sra64() [all …]
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/third_party/skia/third_party/externals/opengl-registry/extensions/KHR/ |
D | KHR_texture_compression_astc_hdr.txt | 1324 int shamt = shamts[mode]; 1325 red <<= shamt; green <<= shamt; blue <<= shamt; scale <<= shamt; 1455 int shamt = (modeval >> 1) ^ 3; 1456 va <<= shamt; vb0 <<= shamt; vb1 <<= shamt; 1457 vc <<= shamt; vd0 <<= shamt; vd1 <<= shamt;
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/third_party/openGLES/extensions/OES/ |
D | OES_texture_compression_astc.txt | 1448 int shamt = shamts[mode]; 1449 red <<= shamt; green <<= shamt; blue <<= shamt; scale <<= shamt; 1579 int shamt = (modeval >> 1) ^ 3; 1580 va <<= shamt; vb0 <<= shamt; vb1 <<= shamt; 1581 vc <<= shamt; vd0 <<= shamt; vd1 <<= shamt;
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/third_party/skia/third_party/externals/opengl-registry/extensions/OES/ |
D | OES_texture_compression_astc.txt | 1435 int shamt = shamts[mode]; 1436 red <<= shamt; green <<= shamt; blue <<= shamt; scale <<= shamt; 1566 int shamt = (modeval >> 1) ^ 3; 1567 va <<= shamt; vb0 <<= shamt; vb1 <<= shamt; 1568 vc <<= shamt; vd0 <<= shamt; vd1 <<= shamt;
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/third_party/openGLES/extensions/KHR/ |
D | KHR_texture_compression_astc_hdr.txt | 1335 int shamt = shamts[mode]; 1336 red <<= shamt; green <<= shamt; blue <<= shamt; scale <<= shamt; 1466 int shamt = (modeval >> 1) ^ 3; 1467 va <<= shamt; vb0 <<= shamt; vb1 <<= shamt; 1468 vc <<= shamt; vd0 <<= shamt; vd1 <<= shamt;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenDAGISel.inc | 7430 /* 14286*/ OPC_RecordChild3, // #2 = $shamt 7441 …PTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) - Complexity = 12 7442 …t: (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) 7461 /* 14339*/ OPC_RecordChild3, // #2 = $shamt 7472 …[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) - Complexity = 12 7473 … Dst: (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) 8250 /* 15705*/ OPC_RecordChild2, // #1 = $shamt 8260 …PTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) - Complexity = 12 8261 …t: (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) 8278 /* 15755*/ OPC_RecordChild2, // #1 = $shamt [all …]
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D | MipsGenMCPseudoLowering.inc | 307 // Operand: shamt
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D | MipsGenGlobalISel.inc | 6001 …:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }… 6005 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 6024 …:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }… 6028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 6047 …P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<… 6051 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 6070 …P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<… 6074 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 11176 …:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }… 11180 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt [all …]
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