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Searched refs:slice_masks (Results 1 – 5 of 5) sorted by relevance

/third_party/mesa3d/src/intel/dev/
Dintel_device_info.h243 uint8_t slice_masks; member
441 return (devinfo->slice_masks & (1U << slice)) != 0; in intel_device_info_slice_available()
Dintel_device_info.c1106 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks)); in reset_masks()
1115 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks); in update_slice_subslice_counts()
1142 assert(devinfo->slice_masks == 1 || devinfo->verx10 >= 125); in update_pixel_pipes()
1258 devinfo->slice_masks |= 1u << s; in update_from_single_slice_topology()
1298 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1299 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
Dintel_device_info_test.h31 assert(__builtin_popcount(devinfo->slice_masks) <= devinfo->max_slices); in verify_device_info()
Dintel_dev_info.c139 n_s += (devinfo.slice_masks & (1u << s)) ? 1 : 0; in main()
/third_party/mesa3d/src/intel/perf/
Dintel_perf.c352 perf->sys_vars.slice_mask = devinfo->slice_masks; in compute_topology_builtins()
390 for (int s = 0; s < util_last_bit(devinfo->slice_masks); s++) { in compute_topology_builtins()