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Searched refs:spills (Results 1 – 25 of 44) sorted by relevance

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/third_party/mesa3d/src/broadcom/compiler/
Dvir.c856 prog_data->tmu_spills = c->spills; in v3d_set_prog_data()
1677 c->spills, in v3d_shaderdb_dump()
1836 if (c->spills == 0 || in v3d_compile()
1840 } else if (c->spills + c->fills < in v3d_compile()
1843 best_spill_fill_count = c->spills + c->fills; in v3d_compile()
1854 c->spills, c->fills); in v3d_compile()
1868 c->spills > 0); in v3d_compile()
1880 c->spills > 0) { in v3d_compile()
1887 c->spills, c->fills); in v3d_compile()
Dvir_register_allocate.c532 c->spills++; in v3d_emit_tmu_spill()
941 return c->spills + c->fills < c->max_tmu_spills; in tmu_spilling_allowed()
1192 if (c->spills + c->fills > c->max_tmu_spills) in v3d_register_allocate()
Dnir_to_vir.c4644 assert(c->spills + c->fills <= c->max_tmu_spills); in v3d_nir_to_vir()
4678 c->spills = 0; in v3d_nir_to_vir()
4689 if (!c->spills && c->last_thrsw != restore_last_thrsw) in v3d_nir_to_vir()
4692 if (c->spills && in v3d_nir_to_vir()
Dv3d_compiler.h798 uint32_t spills, fills, loops; member
/third_party/mesa3d/docs/relnotes/
D22.1.3.rst101 - broadcom/compiler: fix postponed TMU spills with multiple writes
102 - broadcom/compiler: don't predicate postponed spills
D20.1.5.rst48 - pan/mdg: Mask spills from texture write
D22.1.0.rst1450 - broadcom/compiler: define max number of tmu spills for compile strategies
1455 - broadcom/compiler: document that spill_base is used for spills and scratch
1457 - broadcom/compiler: fix register class patching for postponed spills
1462 - broadcom/compiler: increase cost of TMU spills to 10
1463 - broadcom/compiler: disallow TMU spills if max tmu spills is 0
1495 - broadcom/compiler: prefer reconstruction over TMU spills when possible
2179 - nouveau: Handle unaligned tlsBase during spills
/third_party/ffmpeg/libavutil/x86/
Dx86util.asm146 ; spills into %9 and %10
187 ; spills into %9 and %10
220 ; spills into %17 and %18
/third_party/e2fsprogs/
D0012-tests-fix-ACL-printing-tests.patch13 this also spills xattrs for "acl_dir/file" into an external xattr
/third_party/openssl/test/recipes/30-test_evp_data/
Devpmac_poly1305.txt167 # 4th power of the key spills to 131th bit in SIMD key setup
/third_party/mesa3d/src/asahi/compiler/
Dagx_compiler.h414 unsigned spills; member
/third_party/mesa3d/src/panfrost/midgard/
Dcompiler.h256 unsigned spills; member
Dmidgard_ra.c1019 ctx->spills++; in mir_spill_register()
/third_party/libunwind/doc/
Dlibunwind-dynamic.tex337 spills register \Var{reg} to a frame-pointer-relative location. The
343 spills register \Var{reg} to a stack-pointer-relative location. The
/third_party/node/deps/v8/src/wasm/baseline/
Dliftoff-assembler.cc552 ZoneVector<int>* slots, LiftoffRegList* spills, in GetTaggedSlotsForOOLCode() argument
561 spills->set(slot.reg()); in GetTaggedSlotsForOOLCode()
/third_party/mesa3d/src/panfrost/bifrost/
Dbi_ra.c684 ctx->spills++; in bi_spill_register()
Dcompiler.h816 unsigned spills; member
/third_party/mesa3d/src/intel/compiler/
Dbrw_compiler.h1544 uint32_t spills; member
/third_party/python/Lib/test/decimaltestdata/
DdqSubtract.decTest615 -- edge case spills
DddSubtract.decTest615 -- edge case spills
Dsubtract.decTest785 -- edge case spills
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td402 // The fast register allocator used during -O0 inserts spills to cover any VRegs
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME.txt381 that it's callee save, and spills it directly to the stack.
/third_party/skia/src/core/
DSkVM.cpp3433 int spills = 0; in jit() local
3443 spills = 0x7fff'ffff; in jit()
3449 spills += needs_spill(v) ? 1 : 0; in jit()
3453 if (min_spills > spills) { in jit()
3454 min_spills = spills; in jit()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DREADME-SSE.txt203 It also exposes some other problems. See MOV32ri -3 and the spills.

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