Searched refs:src1_neg (Results 1 – 10 of 10) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 67 uint32_t src1_neg : 1; member
565 .neg = instr->src1_neg, in print_instr()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 106 bits<1> src1_neg;
109 let Word0{25} = src1_neg;
|
| D | R600ExpandSpecialInstrs.cpp | 279 SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_neg); in runOnMachineFunction()
|
| D | R600InstrInfo.cpp | 1304 OPERAND_CASE(R600::OpName::src1_neg) in getSlotedOps()
1343 R600::OpName::src1_neg, in buildSlotOfVectorInstruction()
1427 FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg); in getFlagOp()
|
| D | R600Instructions.td | 121 let src1_neg = 0;
150 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
156 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
190 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
196 "$src1_neg$src1$src1_rel, "
|
| D | EvergreenInstructions.td | 483 let src1_neg = 0;
|
| D | VOPInstructions.td | 588 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
|
| D | R600ISelLowering.cpp | 2273 TII->getOperandIdx(Opcode, R600::OpName::src1_neg), in PostISelFolding()
|
| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_optimize.c | 590 unsigned src1_neg = inst_add->U.I.SrcReg[1].Negate & dstmask; in peephole_add_presub_add() local
608 if (inst_add->U.I.SrcReg[1].Negate && src1_neg != dstmask) in peephole_add_presub_add()
|
| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 4723 bool src1_neg = ctx->src[1].neg; in tgsi_op2_s() local
4724 if (op == ALU_OP2_ADD_INT && src1_neg) { in tgsi_op2_s()
4725 src1_neg = false; in tgsi_op2_s()
4746 alu.src[1].neg = src1_neg; in tgsi_op2_s()
|