| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_surface.c | 100 config.info.surf_index = &ws->surf_index_color; in amdgpu_surface_init()
104 config.info.surf_index = NULL; in amdgpu_surface_init()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_fs_generator.cpp | 381 const uint32_t surf_index = inst->target; in fire_fb_write() local
387 surf_index, in fire_fb_write()
448 const unsigned surf_index = inst->target; in generate_fb_read() local
450 gfx9_fb_READ(p, dst, payload, surf_index, in generate_fb_read()
949 struct brw_reg surf_index) in generate_get_buffer_size() argument
952 assert(surf_index.file == BRW_IMMEDIATE_VALUE); in generate_get_buffer_size()
980 surf_index.ud, in generate_get_buffer_size()
1522 uint32_t surf_index = index.ud; in generate_uniform_pull_constant_load() local
1529 read_offset, surf_index); in generate_uniform_pull_constant_load()
1544 const uint32_t surf_index = index.ud; in generate_uniform_pull_constant_load_gfx7() local
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| D | brw_vec4_nir.cpp | 460 src_reg surf_index = get_nir_ssbo_intrinsic_index(instr); in nir_emit_intrinsic() local
508 emit_untyped_write(bld, surf_index, offset_reg, val_reg, in nir_emit_intrinsic()
520 src_reg surf_index = get_nir_ssbo_intrinsic_index(instr); in nir_emit_intrinsic() local
528 src_reg read_result = emit_untyped_read(bld, surf_index, offset_reg, in nir_emit_intrinsic()
615 src_reg surf_index; in nir_emit_intrinsic() local
624 surf_index = brw_imm_ud(index); in nir_emit_intrinsic()
630 surf_index = src_reg(this, glsl_type::uint_type); in nir_emit_intrinsic()
631 emit(MOV(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int32, in nir_emit_intrinsic()
633 surf_index = emit_uniformize(surf_index); in nir_emit_intrinsic()
673 surf_index, in nir_emit_intrinsic()
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| D | brw_vec4_generator.cpp | 1273 uint32_t surf_index = index.ud; in generate_pull_constant_load() local
1315 brw_dp_read_desc(devinfo, surf_index, in generate_pull_constant_load()
1326 struct brw_reg surf_index) in generate_get_buffer_size() argument
1329 assert(surf_index.type == BRW_REGISTER_TYPE_UD && in generate_get_buffer_size()
1330 surf_index.file == BRW_IMMEDIATE_VALUE); in generate_get_buffer_size()
1336 surf_index.ud, in generate_get_buffer_size()
1350 struct brw_reg surf_index, in generate_pull_constant_load_gfx7() argument
1354 assert(surf_index.type == BRW_REGISTER_TYPE_UD); in generate_pull_constant_load_gfx7()
1356 if (surf_index.file == BRW_IMMEDIATE_VALUE) { in generate_pull_constant_load_gfx7()
1364 brw_sampler_desc(devinfo, surf_index.ud, in generate_pull_constant_load_gfx7()
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| D | brw_fs.h | 117 const fs_reg &surf_index,
511 struct brw_reg surf_index);
525 struct brw_reg surf_index,
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| D | brw_vec4_visitor.cpp | 734 src_reg surf_index, in emit_pull_constant_load_reg() argument
758 surf_index, in emit_pull_constant_load_reg()
764 surf_index, in emit_pull_constant_load_reg()
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| D | brw_vec4.h | 274 src_reg surf_index,
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| D | brw_fs_nir.cpp | 4130 fs_reg surf_index = image; in get_nir_image_intrinsic_image() local
4132 return bld.emit_uniformize(surf_index); in get_nir_image_intrinsic_image()
4756 fs_reg surf_index; in nir_emit_intrinsic() local
4759 surf_index = brw_imm_ud(index); in nir_emit_intrinsic()
4765 surf_index = vgrf(glsl_type::uint_type); in nir_emit_intrinsic()
4766 bld.MOV(surf_index, get_nir_src(instr->src[0])); in nir_emit_intrinsic()
4767 surf_index = bld.emit_uniformize(surf_index); in nir_emit_intrinsic()
4775 VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index, in nir_emit_intrinsic()
4832 packed_consts, surf_index, in nir_emit_intrinsic()
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| D | brw_fs.cpp | 168 const fs_reg &surf_index, in VARYING_PULL_CONSTANT_LOAD() argument
195 vec4_result, surf_index, vec4_offset, in VARYING_PULL_CONSTANT_LOAD()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_surface.h | 407 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ member
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| D | ac_surface.c | 926 if ((info->gfx_level >= GFX7 || config->info.levels == 1) && config->info.surf_index && in gfx6_surface_settings()
936 AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1; in gfx6_surface_settings()
1859 if (config->info.surf_index && in->swizzleMode >= ADDR_SW_64KB_Z_T && !out.mipChainInTail && in gfx9_compute_miptree()
1867 xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1; in gfx9_compute_miptree()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 18.2.8.rst | 132 - radv: don't set surf_index for stencil-only images
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| D | 18.3.2.rst | 205 - radv: don't set surf_index for stencil-only images
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| D | 19.0.0.rst | 2073 - radv: don't set surf_index for stencil-only images
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 531 image->info.surf_index = NULL; in radv_patch_image_from_extra_info()
1879 image->info.surf_index = &device->image_mrt_offset_counter; in radv_image_create()
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