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Searched refs:v16i1 (Results 1 – 25 of 34) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td171 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
203 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
206 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
227 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
230 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
253 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
258 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
263 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
270 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
277 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
[all …]
DX86CallingConv.td84 // Promote v8i1/v16i1/v32i1 arguments to i32.
85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
158 // Promote v16i1 arguments to i16.
159 CCIfType<[v16i1], CCPromoteToType<i16>>,
229 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
537 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
822 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
1001 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
DX86TargetTransformInfo.cpp1287 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, in getCastInstrCost()
1288 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, in getCastInstrCost()
1295 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, in getCastInstrCost()
1296 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, in getCastInstrCost()
1346 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
1347 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
1360 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1369 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
2700 { ISD::AND, MVT::v16i1, 9 }, in getArithmeticReductionCost()
2706 { ISD::OR, MVT::v16i1, 9 }, in getArithmeticReductionCost()
DX86InstrAVX512.td168 def v16i1_info : X86KVectorVTInfo<VK16, VK16WM, v16i1>;
430 [(set VR512:$dst, (vselect (v16i1 VK16WM:$mask),
2836 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2852 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2854 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2862 def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))),
2864 def : Pat<(i64 (zext (i16 (bitconvert (v16i1 VK16:$src))))),
2866 def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))),
2868 def : Pat<(i64 (anyext (i16 (bitconvert (v16i1 VK16:$src))))),
2905 def : Pat<(v16i1 (bitconvert (loadi16 addr:$src))),
[all …]
DX86RegisterInfo.td600 def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
618 def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
DX86FrameLowering.cpp2037 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in assignCalleeSavedSpillSlots()
2118 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in spillCalleeSavedRegisters()
2199 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in restoreCalleeSavedRegisters()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTypes.def49 X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \
77 X(v16i1, 1, 1, 0, 0, 1, 1, v16i1) \
78 X(v16i8, 1, 1, 0, 1, 0, 1, v16i1) \
DIceInstX86.def62 X(v16i1, i8, "?", "", "", "", "b", "bw", "", "", "") \
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp145 testSelect<v16si8, v16i1>(TotalTests, Passes, Failures); in main()
146 testSelect<v16ui8, v16i1>(TotalTests, Passes, Failures); in main()
149 testSelectI1<v16i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops_main.cpp175 testInsertElement<v16i1>(TotalTests, Passes, Failures); in main()
186 testExtractElement<v16i1>(TotalTests, Passes, Failures); in main()
197 testShuffleVector<v16i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops.def31 X(v16i1, v16ui8, 16) \
Dvectors.def32 X(v16i1, v16si8, 16)
Dtest_icmp_main.cpp346 testsVecI1<v16i1>(TotalTests, Passes, Failures); in main()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h64 v16i1 = 18, // 16 x i1 enumerator
330 SimpleTy == MVT::v16i1); in is16BitVector()
432 case v16i1: in getVectorElementType()
585 case v16i1: in getVectorNumElements()
712 case v16i1: in getSizeInBits()
927 if (NumElements == 16) return MVT::v16i1; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc3338 /* 6734*/ /*SwitchType*/ 55, MVT::v16i1,// ->6791
3353 MVT::v16i1, 2/*#Ops*/, 9, 10,
3354 … // Src: (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) - Complexity = 3
3355 …:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i3…
10055 /* 21221*/ OPC_CheckType, MVT::v16i1,
10060 MVT::v16i1, 5/*#Ops*/, 1, 2, 3, 4, 0,
10061 …// Src: (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, (ARMvcmp:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, …
10062 …// Dst: (MVE_VCMPi8r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, GPR:{ *:[i32] }:$v2, 0:{ *:[i32] }, 1:{…
10067 /* 21248*/ OPC_CheckType, MVT::v16i1,
10072 MVT::v16i1, 5/*#Ops*/, 1, 2, 3, 4, 0,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc2581 …1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
2615 …1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
2643 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
3474 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32…
3547 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32…
3670 …i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32…
3801 … (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KANDWrr:{ *:[v16i1] …
4037 …1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32…
5048 …2i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32…
5121 …4i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32…
[all …]
DX86GenCallingConv.inc266 if (LocVT == MVT::v16i1 ||
511 if (LocVT == MVT::v16i1) {
821 LocVT == MVT::v16i1 ||
1509 if (LocVT == MVT::v16i1) {
1887 LocVT == MVT::v16i1 ||
2358 LocVT == MVT::v16i1 ||
2756 if (LocVT == MVT::v16i1) {
3037 if (LocVT == MVT::v16i1) {
3607 if (LocVT == MVT::v16i1) {
3821 if (LocVT == MVT::v16i1) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td329 def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b00, "i", ?>;
337 def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b00, "s", 0b0>;
341 def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b00, "u", 0b1>;
352 def MVE_v16p8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b11, "p", 0b0>;
3776 def i8 : Pat<(v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)),
3777 (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>;
3783 def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)))),
3784 …(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1)…
3792 def i8 : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)),
3793 … (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc))>;
[all …]
DARMTargetTransformInfo.cpp456 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } in getCmpSelInstrCost()
DARMRegisterInfo.td358 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1], 32, (add VPR)> {
DARMISelLowering.cpp406 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1}; in addMVEVectorTypes()
7770 case MVT::v16i1: in getVectorTyFromPredicateVector()
7798 if (VT != MVT::v16i1) in PromoteMVEPredVector()
7799 RecastV1 = DAG.getNode(ARMISD::PREDICATE_CAST, dl, MVT::v16i1, Pred); in PromoteMVEPredVector()
9075 assert((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemVT == MVT::v16i1) && in LowerPredicateLoad()
9095 SDValue Pred = DAG.getNode(ARMISD::PREDICATE_CAST, dl, MVT::v16i1, Load); in LowerPredicateLoad()
9096 if (MemVT != MVT::v16i1) in LowerPredicateLoad()
9105 assert((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemVT == MVT::v16i1) && in LowerPredicateStore()
9115 if (MemVT != MVT::v16i1) { in LowerPredicateStore()
9122 Build = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i1, Ops); in LowerPredicateStore()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp609 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 }, in getCmpSelInstrCost()
611 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
614 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost } in getCmpSelInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td306 [v16i1, v32i1, v16i1]>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp163 case MVT::v16i1: return VectorType::get(Type::getInt1Ty(Context), 16); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td39 def v16i1 : ValueType<16, 18>; // 16 x i1 vector value

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