Searched refs:v1b (Results 1 – 9 of 9) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_to_hw_instr.cpp | 150 Definition(v0_lo, v1b), Definition(v1_lo, v1b),
151 Operand(v1_lo, v1b), Operand(v0_lo, v1b));
160 Operand(v1_lo, v1b), Operand(v0_lo, v1b));
170 Definition(v0_lo, v3b), Operand(v1_lo, v1b),
171 Operand(v0_lo, v1b), Operand(v2_lo, v1b));
184 Operand(v1_lo, v1b), Operand(v0_lo, v1b),
185 Operand(v2_lo, v1b), Operand(v3_lo, v1b));
198 Operand(v0_lo, v1b), Operand(v0_lo, v1b),
199 Operand(v0_lo, v1b), Operand(v0_lo, v1b));
207 Definition(v1_lo, v1b), Definition(v0_lo, v1b),
[all …]
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| D | test_regalloc.cpp | 156 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::zero());
174 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::c32(4u));
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| D | test_sdwa.cpp | 40 … sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa();
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.3.rst | 123 - aco: use v1b/v2b for ds_read_u8/ds_read_u16
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| D | 21.3.0.rst | 3582 - aco/ra: allow v1b operands with 16-bit instructions
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| D | 21.2.0.rst | 4451 - aco: use v1b/v2b for ds_read_u8/ds_read_u16
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 513 if (src.regClass() == v1b) { in emit_reduction()
1086 assert(dst.regClass() == v1b || dst.regClass() == v2b); in copy_constant()
1093 if (dst.regClass() == v1b && use_sdwa) { in copy_constant()
1274 } else if (def.regClass() == v1b && ctx->program->gfx_level >= GFX11) { in do_copy()
1321 swap_subdword_gfx11(bld, def, Operand(def_other_half.advance(op.physReg().byte() & 1), v1b)); in swap_subdword_gfx11()
1350 tmp.op = Operand(op, v1b); in do_swap()
1351 tmp.def = Definition(def, v1b); in do_swap()
2237 assert(dst.regClass() == v2b || dst.regClass() == v1b || op.regClass() == v2b || in lower_to_hw_instr()
2238 op.regClass() == v1b); in lower_to_hw_instr()
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| D | aco_ir.h | 327 v1b = v1 | (1 << 7), enumerator
394 static constexpr RegClass v1b{RegClass::v1b};
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| D | aco_instruction_selection.cpp | 1492 if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { in visit_alu_instr()
1645 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { in visit_alu_instr()
1661 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { in visit_alu_instr()
1677 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { in visit_alu_instr()
2835 tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), tmp, Operand::zero()); in visit_alu_instr()
8661 if (src.regClass() == v1b || src.regClass() == v2b) { in visit_intrinsic()
8666 bld.def(src.regClass() == v1b ? v3b : v2b), tmp); in visit_intrinsic()
8709 if (src.regClass() == v1b || src.regClass() == v2b || src.regClass() == v1) { in visit_intrinsic()
8945 } else if (dst.regClass() == v1b) { in visit_intrinsic()
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