v1i32 (reference) in projects: third_party

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:v1i32 (Results 1 – 10 of 10) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
D	MachineValueType.h	`92 v1i32 = 43, // 1 x i32 enumerator 336 SimpleTy == MVT::v2i16 \|\| SimpleTy == MVT::v1i32 \|\| in is32BitVector() 475 case v1i32: in getVectorElementType() 655 case v1i32: in getVectorNumElements() 725 case v1i32: return TypeSize::Fixed(32); in getSizeInBits() 958 if (NumElements == 1) return MVT::v1i32; in getVectorVT()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	AArch64SchedA57.td	347 // D form - v1i8, v1i16, v1i32, v1i64 374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL\|SQR?DMULH)(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v… 410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2… 423 // D form - v1i32, v1i64 438 …yc_1V], (instregex "^(FACGE\|FACGT\|FCMEQ\|FCMGE\|FCMGT\|FCMLE\|FCMLT)(v2f32\|32\|64\|v1i32\|v2i32\|v1i64)")>; 445 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32\|v1i32\|v2i32\|v1i6… 476 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32\|v1i32\|v2i32\|v1i64\|32\|64)")>; 485 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32\|v1i32\|v2i32\|v1i64)")>; 500 // D form - v1i8, v1i16, v1i32, v1i64 514 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP\|RSQRT)(E\|X)(v2f32\|v1i32\|v2i32\|v1i64)")>; [all …]
D	AArch64SchedFalkorDetails.td	591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ\|LE\|GE\|GT\|LT)(v1i32\|v1i64\|v2i32)rz$")>; 598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N\|M\|P\|Z\|A)(S\|U)(v1i32\|v1i64\|v2f32)$")>; 681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S\|U)QADD(v1i8\|v1i16\|v2i16\|v1i32\|v1i64\|v2i32\|v4i… 683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S\|U)(QSHL\|RSHL\|QRSHL)(v1i8\|v1i16\|v1i32\|v1i64\|v2… 685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S\|U)QSUB(v1i8\|v1i16\|v2i16\|v1i32\|v1i64\|v2i32\|v4i… 690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU\|US)QADD(v1i8\|v1i16\|v2i16\|v1i32\|v1i64\|v2i32\|v… 694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8\|v1i16\|v1i32\|v1i64\|v2i32\|v4i16\|v8i8)$"… 695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8\|v1i16\|v1i32\|v1i64)$")>; 703 … (instregex "^SQR?DMULH(v8i8\|v4i16\|v1i32\|v2i32\|v1i16)(_indexed)?$")>; 707 … (instregex "^SQRDML(A\|S)H(i16\|i32\|v8i8\|v4i16\|v1i32\|v2i32\|v1i16)(_indexed)?$")>; [all …]
D	AArch64SchedKryoDetails.td	147 (instregex "(S\|U)CVTF(v1i32\|v2i32\|v1i64\|v2f32\|d\|s)(_shift)?")>; 213 (instregex "(S\|U\|SU\|US)QADD(v1i8\|v1i16\|v2i16\|v1i32\|v1i64)")>; 231 (instregex "(S\|U)(QSHL\|RSHL\|QRSHL)(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2i32)$")>; 261 (instregex "(S\|U)QSUB(v8i8\|v4i16\|v2i32\|v1i64\|v1i32\|v1i16\|v1i8)")>; 273 (instregex "(S\|U)QXTU?N(v1i8\|v1i16\|v1i32)")>; 693 (instregex "FCM(EQ\|LE\|GE\|GT\|LT)(v1i32\|v1i64)rz")>; 735 (instregex "FCVT((A\|N\|M\|P)(S\|U)\|Z(S\|U)_Int)(v1i32\|v1i64\|v2f32)$")>; 771 (instregex "FCVTZ(S\|U)(v2f32\|v1i32\|v1i64\|v2i32(_shift)?)$")>; 1818 (instregex "SQR?DMULH(v8i8\|v4i16\|v1i32\|v2i32\|v1i16)(_indexed)?")>; 1824 (instregex "SQ(ABS\|NEG)(v1i8\|v1i16\|v1i32\|v1i64)")>;
D	AArch64SchedThunderX2T99.td	`1306 "(v8i8\|v4i16\|v2i32\|v1i8\|v1i16\|v1i32\|v1i64)" # 1335 "(v1i8\|v1i16\|v1i32\|v1i64\|v8i8\|v4i16\|v2i32\|b\|d\|h\|s)")>; 1421 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32\|v1i32\|v2i32\|v1i64)")>; 1458 (instregex "^FMULX?(v2f32\|v1i32\|v2i32\|v1i64\|32\|64)")>; 1468 (instregex "^FML[AS](v2f32\|v1i32\|v2i32\|v1i64)")>;`
D	AArch64InstrFormats.td	6554 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>; 6561 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>; 6566 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, 6573 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst), 6783 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>; 6793 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm, 6806 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm, 6821 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm, 6836 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm, 8212 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an [all …]
D	AArch64ISelLowering.cpp	`13048 if (VT == MVT::v1i8 \|\| VT == MVT::v1i16 \|\| VT == MVT::v1i32 \|\| in getPreferredVectorAction()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
D	ValueTypes.cpp	`188 case MVT::v1i32: return VectorType::get(Type::getInt32Ty(Context), 1); in getTypeForEVT()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
D	ValueTypes.td	`67 def v1i32 : ValueType<32 , 43>; // 1 x i32 vector value`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
D	Intrinsics.td	`257 def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32`