v2i16 (reference) in projects: third_party

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:v2i16 (Results 1 – 25 of 64) sorted by relevance

12 3

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
D	MipsGenDAGISel.inc	542 /* 884/ OPC_CheckChild1Type, MVT::v2i16, 554 …// Src: (st DSPR:{ :[v2i16] }:$val, addr:{ :[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predic… 555 …// Dst: (SW (COPY_TO_REGCLASS:{ :[i32] } DSPR:{ :[v2i16] }:$val, GPR32:{ :[i32] }), addr:{ :[i… 1327 / 2361/ /SwitchType/ 25, MVT::v2i16,// ->2388 1335 MVT::v2i16, 2/#Ops/, 4, 5, 1336 …// Src: (ld:{ :[v2i16] } addr:{ :[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> -… 1337 … // Dst: (COPY_TO_REGCLASS:{ :[v2i16] } (LW:{ :[i32] } addr:{ :[iPTR] }:$a), DSPR:{ :[i32] }) 7102 …rinsic_w_chain:{ :[i32] } 4108:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$… 7103 … // Dst: (MULEQ_S_W_PHL:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) 7109 …rinsic_w_chain:{ :[i32] } 4108:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$… [all …]
D	MipsGenGlobalISel.inc	989 …// (add:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (ADDQ_PH:{ :[v2i16] } … 1360 …// (sub:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (SUBQ_PH:{ :[v2i16] } … 1650 …// (mul:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (MUL_PH:{ :[v2i16] } v… 3167 …// (bitconvert:{ :[i32] } DSPR:{ :[v2i16] }:$src) => (COPY_TO_REGCLASS:{ :[i32] } DSPR:{ :[v… 3189 …// (bitconvert:{ :[f32] } DSPR:{ :[v2i16] }:$src) => (COPY_TO_REGCLASS:{ :[f32] } DSPR:{ :[v… 3240 …// (bitconvert:{ :[v2i16] } GPR32:{ :[i32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i16] } GPR32:{ … 3249 …// (bitconvert:{ :[v2i16] } FGR32:{ :[f32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i16] } FGR32:{ … 4685 … (intrinsic_wo_chain:{ :[v2i16] } 4173:{ :[iPTR] }, (imm:{ :[i32] })<<P:Predicate_immSExt10>>:$… 4706 …intrinsic_wo_chain:{ :[v2i16] } 4173:{ :[iPTR] }, (imm:{ :[i32] })<<P:Predicate_immSExt10>>:$im… 4759 … :[i32] } 4153:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt) => (PRECEQ_W_PHL:{ :[i32] } DSPROpnd:… [all …]
D	MipsGenFastISel.inc	1273 if (RetVT.SimpleTy != MVT::v2i16) 1314 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1733 if (RetVT.SimpleTy != MVT::v2i16) 1773 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2419 if (RetVT.SimpleTy != MVT::v2i16) 2460 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3486 if (RetVT.SimpleTy != MVT::v2i16) 3497 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3514 if (RetVT.SimpleTy != MVT::v2i16) 3525 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
D	MipsDSPInstrInfo.td	1340 def : BitconvertPat<i32, v2i16, GPR32, DSPR>; 1342 def : BitconvertPat<v2i16, i32, DSPR, GPR32>; 1344 def : BitconvertPat<f32, v2i16, FGR32, DSPR>; 1346 def : BitconvertPat<v2i16, f32, DSPR, FGR32>; 1349 def : DSPPat<(v2i16 (load addr:$a)), 1350 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>; 1353 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a), 1363 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>; 1364 def : DSPBinPat<ADDQ_PH, v2i16, add>; 1365 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>; [all …]
D	MipsRegisterInfo.td	`316 def DSPR : GPR32Class<[v4i8, v2i16]>; 474 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;`
D	MipsSEISelLowering.cpp	86 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; in MipsSETargetLowering() 115 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering() 875 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSHLCombine() 932 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) \|\| !Subtarget.hasDSPR2())) in performSRACombine() 944 if (((Ty != MVT::v2i16) \|\| !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) in performSRLCombine() 951 bool IsV216 = (Ty == MVT::v2i16); in isLegalDSPCondCode() 971 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) in performSETCCCombine() 984 if (Ty == MVT::v2i16 \|\| Ty == MVT::v4i8) { in performVSELECTCombine()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
D	AMDGPUCallingConv.td	`21 CCIfInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[ 31 CCIfNotInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[ 115 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[ 120 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>, 133 CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[`
D	SIRegisterInfo.td	230 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 259 def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 358 def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>; 391 def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 413 def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 425 def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 433 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 441 def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 446 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 452 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, [all …]
D	SIInstructions.td	`931 (v2i16 (EXTRACT_SUBREG v4i16:$vec, sub0)) 936 (v2i16 (EXTRACT_SUBREG v4i16:$vec, sub1)) 980 def : BitConvert <v2i16, i32, SReg_32>; 981 def : BitConvert <i32, v2i16, SReg_32>; 984 def : BitConvert <v2i16, v2f16, SReg_32>; 985 def : BitConvert <v2f16, v2i16, SReg_32>; 988 def : BitConvert <v2i16, f32, SReg_32>; 989 def : BitConvert <f32, v2i16, SReg_32>; 1797 (v2i16 (build_vector (i16 0), (i16 SReg_32:$src1))), 1802 (v2i16 (build_vector (i16 SReg_32:$src0), (i16 undef))), [all …]`
D	SIInstrInfo.td	301 !if(!eq(SrcVT.Value, v2i16.Value), 1, 1486 !if(!eq(VT.Value, v2i16.Value), 1537 !if(!eq(VT.Value, v2i16.Value), 1555 !if(!eq(SrcVT.Value, v2i16.Value), 1, 2252 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>; 2256 def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>; 2257 def VOP_V2I16_F32_F32 : VOPProfile <[v2i16, f32, f32, untyped]>; 2258 def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32, untyped]>; 2303 def VOP_I32_V2I16_V2I16_I32 : VOPProfile <[i32, v2i16, v2i16, i32]>; 2311 def VOP_V4F32_V2I16_V2I16_V4F32 : VOPProfile <[v4f32, v2i16, v2i16, v4f32]>; [all …]
D	FLATInstructions.td	824 def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_flat, v2i16>; 826 def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_flat, v2i16>; 828 def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16_HI, load_d16_hi_flat, v2i16>; 831 def : FlatLoadPat_D16 <FLAT_LOAD_UBYTE_D16, az_extloadi8_d16_lo_flat, v2i16>; 833 def : FlatLoadPat_D16 <FLAT_LOAD_SBYTE_D16, sextloadi8_d16_lo_flat, v2i16>; 835 def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2i16>; 884 def : FlatSignedLoadPat_D16 <GLOBAL_LOAD_UBYTE_D16_HI, az_extloadi8_d16_hi_global, v2i16>; 886 def : FlatSignedLoadPat_D16 <GLOBAL_LOAD_SBYTE_D16_HI, sextloadi8_d16_hi_global, v2i16>; 888 def : FlatSignedLoadPat_D16 <GLOBAL_LOAD_SHORT_D16_HI, load_d16_hi_global, v2i16>; 891 def : FlatSignedLoadPat_D16 <GLOBAL_LOAD_UBYTE_D16, az_extloadi8_d16_lo_global, v2i16>; [all …]
D	SIISelLowering.cpp	155 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass); in SITargetLowering() 194 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); in SITargetLowering() 232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering() 317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering() 322 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering() 525 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) { in SITargetLowering() 549 setOperationAction(ISD::Constant, MVT::v2i16, Legal); in SITargetLowering() 552 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal); in SITargetLowering() 555 setOperationAction(ISD::STORE, MVT::v2i16, Promote); in SITargetLowering() 556 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32); in SITargetLowering() [all …]
D	DSInstructions.td	`676 def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>; 678 def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>; 680 def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>; 683 def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>; 685 def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>; 687 def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;`
D	BUFInstructions.td	1232 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v2i16, "BUFFER_LOAD_FORMAT_D16_XY">; 1239 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2i16, "BUFFER_LOAD_DWORD">; 1314 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2i16, "BUFFER_STORE_FORMAT_D16_XY">; 1321 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2i16, "BUFFER_STORE_DWORD">; 1594 …dPat_D16<BUFFER_LOAD_SHORT_D16_HI_OFFEN, BUFFER_LOAD_SHORT_D16_HI_OFFSET, v2i16, load_d16_hi_priva… 1595 …dPat_D16<BUFFER_LOAD_UBYTE_D16_HI_OFFEN, BUFFER_LOAD_UBYTE_D16_HI_OFFSET, v2i16, az_extloadi8_d16_… 1596 …dPat_D16<BUFFER_LOAD_SBYTE_D16_HI_OFFEN, BUFFER_LOAD_SBYTE_D16_HI_OFFSET, v2i16, sextloadi8_d16_hi… 1601 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_SHORT_D16_OFFEN, BUFFER_LOAD_SHORT_D16_OFFSET, v2i16, lo… 1602 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_UBYTE_D16_OFFEN, BUFFER_LOAD_UBYTE_D16_OFFSET, v2i16, az… 1603 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_SBYTE_D16_OFFEN, BUFFER_LOAD_SBYTE_D16_OFFSET, v2i16, se…
D	VOP3PInstructions.td	`78 …(add (v2i16 (VOP3PMods0 v2i16:$src0, i32:$src0_modifiers, i1:$clamp)), NegSubInlineConstV216:$src1…`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
D	HexagonCallingConv.td	`15 CCIfType<[i32,v2i16,v4i8], 39 CCIfType<[i32,v2i16,v4i8], 67 CCIfType<[i32,v2i16,v4i8],`
D	HexagonISelLowering.cpp	610 VT == MVT::v2i16 \|\| VT == MVT::v2i32 \|\| VT == MVT::v4i8 \|\| in getPostIndexedAddressParts() 872 if (OpTy == MVT::v2i16 \|\| OpTy == MVT::v4i8) { in LowerSETCC() 930 if (OpTy == MVT::v2i16 \|\| OpTy == MVT::v4i8) { in LowerVSELECT() 1324 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1372 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering() 1523 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering() 1524 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering() 1525 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering() 1531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering() 1536 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering() [all …]
D	HexagonPatterns.td	84 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>; 438 // All of these are bitcastable to one another: i32, v2i16, v4i8. 439 defm: NopCast_pat<i32, v2i16, IntRegs>; 441 defm: NopCast_pat<v2i16, v4i8, IntRegs>; 480 def: Pat<(v2i16 (sext V2I1:$Pu)), (S2_vtrunehb (C2_mask V2I1:$Pu))>; 489 def: Pat<(v2i16 (azext V2I1:$Pu)), 508 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)), 524 def: Pat<(v2i16 (trunc V2I32:$Rs)), 1354 def: OpR_RR_pat<A2_svaddh, Add, v2i16, V2I16>; 1355 def: OpR_RR_pat<A2_svsubh, Sub, v2i16, V2I16>; [all …]
D	HexagonRegisterInfo.td	`336 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, 356 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	AArch64TargetTransformInfo.cpp	335 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost() 338 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost() 359 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost() 362 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost() 376 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost() 379 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost() 390 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost() 393 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
/third_party/mesa3d/src/panfrost/bifrost/valhall/test/
D	assembler-cases.txt	`52 40 db 05 04 00 c1 a1 00 MKVEC.v2i16 r1, ^r0.h00, 0x3C000000.h10 88 42 14 00 13 00 c2 11 01 IADD_IMM.v2i16 r2, ^r2, #0x130014 142 42 c0 05 00 00 c2 a1 00 MKVEC.v2i16 r2, ^r2.h00, 0x0.h00 143 77 c0 05 00 00 c2 a1 00 MKVEC.v2i16 r2, ^r55.h00, 0x0.h00 144 77 c0 05 10 00 c2 a1 00 MKVEC.v2i16 r2, ^r55.h10, 0x0.h00 145 c0 77 05 00 00 c2 a1 00 MKVEC.v2i16 r2, 0x0.h00, ^r55.h00 146 c0 77 05 04 00 c2 a1 00 MKVEC.v2i16 r2, 0x0.h00, ^r55.h10`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
D	MachineValueType.h	`83 v2i16 = 35, // 2 x i16 enumerator 336 SimpleTy == MVT::v2i16 \|\| SimpleTy == MVT::v1i32 \|\| in is32BitVector() 461 case v2i16: in getVectorElementType() 638 case v2i16: in getVectorNumElements() 722 case v2i16: in getSizeInBits() 948 if (NumElements == 2) return MVT::v2i16; in getVectorVT()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
D	IntrinsicsNVVM.td	`2141 "llvm.nvvm.suld.1d.v2i16.clamp">; 2186 "llvm.nvvm.suld.1d.array.v2i16.clamp">; 2231 "llvm.nvvm.suld.2d.v2i16.clamp">; 2276 "llvm.nvvm.suld.2d.array.v2i16.clamp">; 2321 "llvm.nvvm.suld.3d.v2i16.clamp">; 2367 "llvm.nvvm.suld.1d.v2i16.trap">; 2412 "llvm.nvvm.suld.1d.array.v2i16.trap">; 2457 "llvm.nvvm.suld.2d.v2i16.trap">; 2502 "llvm.nvvm.suld.2d.array.v2i16.trap">; 2547 "llvm.nvvm.suld.3d.v2i16.trap">; [all …]`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
D	ARMTargetTransformInfo.cpp	`248 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost() 249 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost() 280 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost() 281 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost() 373 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 }, in getCastInstrCost() 374 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 }, in getCastInstrCost()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
D	X86TargetTransformInfo.cpp	1375 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, in getCastInstrCost() 1584 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost() 1619 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB in getCastInstrCost() 1624 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, in getCastInstrCost() 1632 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW in getCastInstrCost() 2577 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16 in getArithmeticReductionCost() 2607 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". in getArithmeticReductionCost()

12 3