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Searched refs:v32i32 (Results 1 – 18 of 18) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td88 CCIfType<[v32i32,v64i16,v128i8],
94 CCIfType<[v32i32,v64i16,v128i8],
99 CCIfType<[v32i32,v64i16,v128i8],
105 CCIfType<[v32i32,v64i16,v128i8],
120 CCIfType<[v32i32,v64i16,v128i8],
125 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsics.td263 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
264 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
267 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
268 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
271 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
272 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
275 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
276 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
304 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
305 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
[all …]
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
46 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
47 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td292 [v16i32, v32i32, v16i32]>;
299 [v32i32, v64i32, v32i32]>;
DHexagonISelLoweringHVX.cpp17 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
18 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
30 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
46 addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
201 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
DHexagonISelDAGToDAGHVX.cpp2213 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
2227 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
DHexagonISelDAGToDAG.cpp114 case MVT::v32i32: in SelectIndexedLoad()
504 case MVT::v32i32: in SelectIndexedStore()
DHexagonInstrInfo.cpp2666 case MVT::v32i32: in isValidAutoIncImm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h99 v32i32 = 50, // 32 x i32 enumerator
376 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
482 case v32i32: in getVectorElementType()
576 case v32i32: in getVectorNumElements()
806 case v32i32: in getSizeInBits()
965 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td586 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
591 def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
647 def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
678 def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
DSIInstructions.td951 i32, v32i32, Index, !cast<SubRegIndex>(sub#Index)
955 i32, v32i32, Index, !cast<SubRegIndex>(sub#Index)
1058 def : BitConvert <v32i32, v32f32, VReg_1024>;
1059 def : BitConvert <v32f32, v32i32, VReg_1024>;
DR600ISelLowering.cpp114 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Custom); in R600TargetLowering()
119 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
DAMDGPUISelLowering.cpp92 AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
192 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32); in AMDGPUTargetLowering()
299 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom); in AMDGPUTargetLowering()
DSIInstrInfo.td2316 def VOP_V32I32_I32_I32_V32I32 : VOPProfile <[v32i32, i32, i32, v32i32]>;
DSIISelLowering.cpp162 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass); in SITargetLowering()
183 setOperationAction(ISD::LOAD, MVT::v32i32, Custom); in SITargetLowering()
192 setOperationAction(ISD::STORE, MVT::v32i32, Custom); in SITargetLowering()
199 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand); in SITargetLowering()
204 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand); in SITargetLowering()
263 MVT::v32i32, MVT::v32f32 }) { in SITargetLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp195 case MVT::v32i32: return VectorType::get(Type::getInt32Ty(Context), 32); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td74 def v32i32 : ValueType<1024,50>; // 32 x i32 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td262 def llvm_v32i32_ty : LLVMType<v32i32>; // 32 x i32