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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td230 [(set v4f64:$FRT, (vselect v4i1:$FRA,
236 [(set v4f32:$FRT, (vselect v4i1:$FRA,
242 [(set v4i1:$FRT, (vselect v4i1:$FRA,
243 v4i1:$FRC, v4i1:$FRB))]>;
269 [(set v4i1:$dst,
270 (select i1:$cond, v4i1:$T, v4i1:$F))]>;
346 [/* (set v4i1:$FRT, v4i1:$FRB) */]>;
402 [(set v4i1:$FRT,
403 (PPCqvaligni v4i1:$FRA, v4i1:$FRB,
421 [(set v4i1:$FRT,
[all …]
DPPCCallingConv.td64 CCIfType<[v4f64, v4f32, v4i1],
102 CCIfType<[v4f64, v4f32, v4i1],
161 CCIfType<[v4f64, v4f32, v4i1],
227 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
247 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
DPPCISelLowering.cpp1066 setOperationAction(ISD::AND , MVT::v4i1, Legal); in PPCTargetLowering()
1067 setOperationAction(ISD::OR , MVT::v4i1, Legal); in PPCTargetLowering()
1068 setOperationAction(ISD::XOR , MVT::v4i1, Legal); in PPCTargetLowering()
1071 setOperationAction(ISD::SELECT, MVT::v4i1, Expand); in PPCTargetLowering()
1072 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
1074 setOperationAction(ISD::LOAD , MVT::v4i1, Custom); in PPCTargetLowering()
1075 setOperationAction(ISD::STORE , MVT::v4i1, Custom); in PPCTargetLowering()
1077 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom); in PPCTargetLowering()
1078 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
1079 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
[all …]
DPPCRegisterInfo.td350 def QBRC : RegisterClass<"PPC", [v4i1], 256, (add QFRC)> {
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp70 void testSelect<v4f32, v4i1>(size_t &TotalTests, size_t &Passes, in testSelect()
96 std::cout << vectAsString<v4i1>(Cond) in testSelect()
140 testSelect<v4f32, v4i1>(TotalTests, Passes, Failures); in main()
141 testSelect<v4si32, v4i1>(TotalTests, Passes, Failures); in main()
142 testSelect<v4ui32, v4i1>(TotalTests, Passes, Failures); in main()
147 testSelectI1<v4i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops_main.cpp173 testInsertElement<v4i1>(TotalTests, Passes, Failures); in main()
184 testExtractElement<v4i1>(TotalTests, Passes, Failures); in main()
195 testShuffleVector<v4i1>(TotalTests, Passes, Failures); in main()
Dtest_vector_ops.def29 X(v4i1, v4ui32, 4) \
Dvectors.def30 X(v4i1, v4si32, 4) \
Dtest_icmp_main.cpp344 testsVecI1<v4i1>(TotalTests, Passes, Failures); in main()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTypes.def47 X(v4i1, 4, 1, 4, i1, "<4 x i1>", "v4i1") \
75 X(v4i1, 1, 1, 0, 0, 1, 1, v4i1) \
80 X(v4i32, 1, 1, 0, 1, 0, 1, v4i1) \
81 X(v4f32, 1, 0, 1, 0, 0, 1, v4i1) \
DIceInstX86.def60 X(v4i1, i32, "?", "", "", "", "d", "dq", "", "", "") \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc3374 /* 6848*/ /*SwitchType*/ 55, MVT::v4i1,// ->6905
3389 MVT::v4i1, 2/*#Ops*/, 9, 10,
3390 … // Src: (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) - Complexity = 3
3391 … *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i3…
10263 /* 21681*/ OPC_CheckType, MVT::v4i1,
10268 MVT::v4i1, 5/*#Ops*/, 1, 2, 3, 4, 0,
10269 …// Src: (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, (ARMvcmp:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1, (AR…
10270 …// Dst: (MVE_VCMPi32r:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1, GPR:{ *:[i32] }:$v2, 0:{ *:[i32] }, 1:{…
10275 /* 21708*/ OPC_CheckType, MVT::v4i1,
10280 MVT::v4i1, 5/*#Ops*/, 1, 2, 3, 4, 0,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td296 // vectors of 2 values, we make an exception, and use v4i1 instead
331 def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "i", ?>;
332 def MVE_v2i64 : MVEVectorVTInfo<v2i64, ?, v4i1, 0b11, "i", ?>;
339 def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "s", 0b0>;
340 def MVE_v2s64 : MVEVectorVTInfo<v2i64, ?, v4i1, 0b11, "s", 0b0>;
343 def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "u", 0b1>;
344 def MVE_v2u64 : MVEVectorVTInfo<v2i64, ?, v4i1, 0b11, "u", 0b1>;
348 def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, 0b10, "f", ?>;
349 def MVE_v2f64 : MVEVectorVTInfo<v2f64, ?, v4i1, 0b11, "f", ?>;
1096 (v4i1 VCCR:$mask), (v4f32 MQPR:$inactive))),
[all …]
DARMTargetTransformInfo.cpp252 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
454 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc20832 /* 52461*/ OPC_CheckType, MVT::v4i1,
20836 MVT::v4i1, 3/*#Ops*/, 0, 1, 2,
20837 …// Src: (xor:{ *:[v4i1] } (or:{ *:[v4i1] } v4i1:{ *:[v4i1] }:$FRA, v4i1:{ *:[v4i1] }:$FRB), -1:{ *…
20838 … // Dst: (QVFLOGICALb:{ *:[v4i1] } ?:{ *:[v4i1] }:$FRA, ?:{ *:[v4i1] }:$FRB, 8:{ *:[i32] })
20845 /* 52496*/ OPC_CheckType, MVT::v4i1,
20849 MVT::v4i1, 3/*#Ops*/, 0, 1, 2,
20850 …// Src: (xor:{ *:[v4i1] } (xor:{ *:[v4i1] } v4i1:{ *:[v4i1] }:$FRA, v4i1:{ *:[v4i1] }:$FRB), -1:{ …
20851 … // Dst: (QVFLOGICALb:{ *:[v4i1] } ?:{ *:[v4i1] }:$FRA, ?:{ *:[v4i1] }:$FRB, 9:{ *:[i32] })
20856 /* 52526*/ OPC_CheckType, MVT::v4i1,
20860 MVT::v4i1, 3/*#Ops*/, 0, 1, 2,
[all …]
DPPCGenCallingConv.inc47 LocVT == MVT::v4i1) {
258 LocVT == MVT::v4i1) {
504 LocVT == MVT::v4i1) {
652 LocVT == MVT::v4i1) {
761 LocVT == MVT::v4i1) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h62 v4i1 = 16, // 4 x i1 enumerator
430 case v4i1: in getVectorElementType()
616 case v4i1: in getVectorNumElements()
703 case v4i1: return TypeSize::Fixed(4); in getSizeInBits()
925 if (NumElements == 4) return MVT::v4i1; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td169 def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>;
264 (v4i1 VK4:$mask), (iPTR 0))),
290 (v4i1 VK4:$mask), (iPTR 0))),
340 (v4i1 VK4:$mask), (iPTR 0))),
353 (v4i1 VK4:$mask), (iPTR 0))),
DX86TargetTransformInfo.cpp1411 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
1412 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
1442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, in getCastInstrCost()
1443 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, in getCastInstrCost()
1470 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
1471 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
1483 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, in getCastInstrCost()
1484 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, in getCastInstrCost()
2698 { ISD::AND, MVT::v4i1, 5 }, in getArithmeticReductionCost()
2704 { ISD::OR, MVT::v4i1, 5 }, in getArithmeticReductionCost()
DX86RegisterInfo.td598 def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
616 def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
DX86CallingConv.td227 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
535 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
820 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td81 def V4I1: PatLeaf<(v4i1 PredRegs:$R)>;
540 def: OpR_RR_pat<MI, Op, v4i1, V4I1>;
617 def: OpR_RR_pat<A2_vcmpheq, seteq, v4i1, V4I16>;
619 def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>;
621 def: OpR_RR_pat<A2_vcmphgt, setgt, v4i1, V4I16>;
623 def: OpR_RR_pat<A2_vcmphgtu, RevCmp<setult>, v4i1, V4I16>;
625 def: OpR_RR_pat<A2_vcmphgtu, setugt, v4i1, V4I16>;
694 def: OpmR_RR_pat<Outn<A2_vcmpheq>, setne, v4i1, V4I16>;
695 def: OpmR_RR_pat<Outn<A2_vcmphgt>, setle, v4i1, V4I16>;
696 def: OpmR_RR_pat<Outn<A2_vcmphgtu>, setule, v4i1, V4I16>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp97 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
98 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
123 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp161 case MVT::v4i1: return VectorType::get(Type::getInt1Ty(Context), 4); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td37 def v4i1 : ValueType<4 , 16>; // 4 x i1 vector value

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