Home
last modified time | relevance | path

Searched refs:v8i64 (Results 1 – 25 of 27) sorted by relevance

12

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp306 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
489 { ISD::MUL, MVT::v8i64, 1 } in getArithmeticInstrCost()
529 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
530 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
534 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add in getArithmeticInstrCost()
1035 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq in getShuffleCost()
1040 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1049 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1059 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q in getShuffleCost()
[all …]
DX86InstrVecCompiler.td84 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
95 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
140 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>;
149 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>;
156 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>;
DX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
303 CCIfType<[v16f32, v8f64, v16i32, v8i64],
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
747 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrAVX512.td419 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
436 (v8i64 immAllOnesV),
437 (v8i64 immAllZerosV)))]>;
920 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
922 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
949 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
951 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
1397 def : Pat<(v8i64 (X86VBroadcast (v2i64 (X86vzload64 addr:$src)))),
1496 def : Pat<(v8i64 (X86SubVBroadcast (v4i64 VR256X:$src))),
1497 (VINSERTI64x4Zrr (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
[all …]
DX86InstrFragmentsSIMD.td810 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
869 (v8i64 (alignedload node:$ptr))>;
938 return Mgt->getIndex().getValueType() == MVT::v8i64;
973 return Sc->getIndex().getValueType() == MVT::v8i64;
1001 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
DX86ISelLowering.cpp1215 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1448 addRegisterClass(MVT::v8i64, &X86::VR512RegClass); in X86TargetLowering()
1454 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal); in X86TargetLowering()
1455 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal); in X86TargetLowering()
1456 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal); in X86TargetLowering()
1495 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal); in X86TargetLowering()
1496 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal); in X86TargetLowering()
1497 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal); in X86TargetLowering()
1515 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
[all …]
DX86RegisterInfo.td577 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
581 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86ISelDAGToDAG.cpp4043 case MVT::v8i64: in getVPTESTMOpc()
4061 case MVT::v8i64: in getVPTESTMOpc()
4090 case MVT::v8i64: in getVPTESTMOpc()
4120 case MVT::v8i64: in getVPTESTMOpc()
4138 case MVT::v8i64: in getVPTESTMOpc()
4167 case MVT::v8i64: in getVPTESTMOpc()
DX86FastISel.cpp454 case MVT::v8i64: in X86FastEmitLoad()
626 case MVT::v8i64: in X86FastEmitStore()
DX86InstrCompiler.td587 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h110 v8i64 = 60, // 8 x i64 enumerator
370 SimpleTy == MVT::v16i32 || SimpleTy == MVT::v8i64); in is512BitVector()
498 case v8i64: in getVectorElementType()
602 case v8i64: in getVectorNumElements()
794 case v8i64: in getSizeInBits()
977 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp316 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
317 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
318 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
319 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
613 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1463 …dd:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPADDQZrr:{ *:[v8i64]…
2007 …ub:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPSUBQZrr:{ *:[v8i64]…
2474 …ul:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMULLQZrr:{ *:[v8i64…
3786 …nd:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPANDQZrr:{ *:[v8i64]…
5360 …(or:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPORQZrr:{ *:[v8i64]…
6682 …or:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPXORQZrr:{ *:[v8i64]…
8615 …v8i64] } 6356:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESENCZrr…
8672 …v8i64] } 6359:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESENCLAS…
8729 …v8i64] } 6350:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESDECZrr…
8786 …v8i64] } 6353:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESDECLAS…
[all …]
DX86GenCallingConv.inc256 LocVT == MVT::v8i64) {
933 LocVT == MVT::v8i64 ||
1020 LocVT == MVT::v8i64 ||
1149 LocVT == MVT::v8i64 ||
1205 LocVT == MVT::v8i64 ||
1269 LocVT == MVT::v8i64 ||
1582 LocVT == MVT::v8i64 ||
1640 LocVT == MVT::v8i64 ||
1717 LocVT == MVT::v8i64 ||
2005 LocVT == MVT::v8i64 ||
[all …]
DX86GenFastISel.inc169 if (RetVT.SimpleTy != MVT::v8i64)
190 case MVT::v8i64: return fastEmit_ISD_ABS_MVT_v8i64_r(RetVT, Op0, Op0IsKill);
259 case MVT::v8i64: return fastEmit_ISD_ANY_EXTEND_MVT_v8i1_MVT_v8i64_r(Op0, Op0IsKill);
594 if (RetVT.SimpleTy != MVT::v8i64)
612 case MVT::v8i64: return fastEmit_ISD_CTLZ_MVT_v8i64_r(RetVT, Op0, Op0IsKill);
746 if (RetVT.SimpleTy != MVT::v8i64)
770 case MVT::v8i64: return fastEmit_ISD_CTPOP_MVT_v8i64_r(RetVT, Op0, Op0IsKill);
1384 case MVT::v8i64: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i64_r(Op0, Op0IsKill);
1504 case MVT::v8i64: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_MVT_v8i64_r(Op0, Op0IsKill);
1531 if (RetVT.SimpleTy != MVT::v8i64)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp231 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
232 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
233 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
234 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
455 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
DARMRegisterInfo.td547 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
DARMISelDAGToDAG.cpp2267 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST()
2393 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
DARMISelLowering.cpp1535 case MVT::v8i64: in findRepresentativeClass()
1736 if (VT == MVT::v8i64) in getRegClassFor()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp205 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td85 def v8i64 : ValueType<512, 60>; // 8 x i64 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp111 case MVT::v8i64: in SelectIndexedLoad()
501 case MVT::v8i64: in SelectIndexedStore()
DHexagonInstrInfo.cpp2663 case MVT::v8i64: in isValidAutoIncImm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td268 def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc32259 MVT::v8i64, 9/*#Ops*/, 6, 2, 7, 3, 8, 4, 9, 5, 10, // Results = #11
32263 …// Dst: (MVE_VST40_8 (REG_SEQUENCE:{ *:[v8i64] } QQQQPR:{ *:[i32] }, v16i8:{ *:[v16i8] }:$v0, qsub…
32274 MVT::v8i64, 9/*#Ops*/, 6, 2, 7, 3, 8, 4, 9, 5, 10, // Results = #11
32278 …// Dst: (MVE_VST41_8 (REG_SEQUENCE:{ *:[v8i64] } QQQQPR:{ *:[i32] }, v16i8:{ *:[v16i8] }:$v0, qsub…
32289 MVT::v8i64, 9/*#Ops*/, 6, 2, 7, 3, 8, 4, 9, 5, 10, // Results = #11
32293 …// Dst: (MVE_VST42_8 (REG_SEQUENCE:{ *:[v8i64] } QQQQPR:{ *:[i32] }, v16i8:{ *:[v16i8] }:$v0, qsub…
32304 MVT::v8i64, 9/*#Ops*/, 6, 2, 7, 3, 8, 4, 9, 5, 10, // Results = #11
32308 …// Dst: (MVE_VST43_8 (REG_SEQUENCE:{ *:[v8i64] } QQQQPR:{ *:[i32] }, v16i8:{ *:[v16i8] }:$v0, qsub…
32329 MVT::v8i64, 9/*#Ops*/, 6, 2, 7, 3, 8, 4, 9, 5, 10, // Results = #11
32333 …// Dst: (MVE_VST40_16 (REG_SEQUENCE:{ *:[v8i64] } QQQQPR:{ *:[i32] }, v8i16:{ *:[v8i16] }:$v0, qsu…
[all …]

12