| /third_party/node/deps/ngtcp2/ngtcp2/lib/ |
| D | ngtcp2_conn.c | 1043 p->version_info.other_versions = conn->vneg.other_versions; in conn_set_local_transport_params()
1044 p->version_info.other_versionslen = conn->vneg.other_versionslen; in conn_set_local_transport_params()
1270 (*pconn)->vneg.preferred_versions = preferred_versions; in conn_new()
1271 (*pconn)->vneg.preferred_versionslen = settings->preferred_versionslen; in conn_new()
1296 (*pconn)->vneg.other_versions = buf; in conn_new()
1297 (*pconn)->vneg.other_versionslen = in conn_new()
1307 (*pconn)->vneg.other_versions = buf; in conn_new()
1308 (*pconn)->vneg.other_versionslen = in conn_new()
1311 (*pconn)->vneg.other_versions = server_default_other_versions; in conn_new()
1312 (*pconn)->vneg.other_versionslen = sizeof(server_default_other_versions); in conn_new()
[all …]
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| D | ngtcp2_conn.h | 669 } vneg; member
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| /third_party/ffmpeg/libavcodec/arm/ |
| D | mdct_neon.S | 210 vneg.f32 d7, d7 @ R*s-I*c
235 vneg.f32 d7, d7 @ R*s-I*c
286 vneg.f32 q2, q2
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| D | hevcdsp_deblock_neon.S | 42 vneg.s16 q12, q0
148 vneg.s16 q6, q7
248 vneg.s16 q6, q7
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| D | mpegvideo_neon.S | 38 vneg.s16 q13, q14
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| D | rv40dsp_neon.S | 823 vneg.s16 q15, q15
836 vneg.s16 d23, d25 @ -lim_p0q0
851 vneg.s16 d19, d18 @ -diff
859 vneg.s16 q9, q9
860 vneg.s16 q14, q13
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| D | sbrdsp_neon.S | 221 vneg.f32 d18, d1
287 vneg.f32 s15, s15
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| D | vc1dsp_neon.S | 150 vneg.s16 d31, d31 @ t4 = -t4
186 vneg.s16 d17, d17 @ t2 = -t2
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| D | h264dsp_neon.S | 92 vneg.s8 q7, q6
205 vneg.s8 d25, d24
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| D | vp9itxfm_16bpp_neon.S | 995 vneg.s32 d29, d29 @ d29 = out[13]
1004 vneg.s32 d19, d19 @ d19 = out[3]
1015 vneg.s32 d31, d5 @ d31 = out[15]
1016 vneg.s32 d17, d3 @ d17 = out[1]
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | assembler-arm.h | 768 void vneg(const DwVfpRegister dst, const DwVfpRegister src,
770 void vneg(const SwVfpRegister dst, const SwVfpRegister src,
885 void vneg(QwNeonRegister dst, QwNeonRegister src);
886 void vneg(NeonSize size, QwNeonRegister dst, QwNeonRegister src);
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| D | macro-assembler-arm.cc | 2364 vneg(result, left); in CallRecordWriteStub()
2366 vneg(result, result); in CallRecordWriteStub()
2369 vneg(result, right); in CallRecordWriteStub()
2371 vneg(result, result); in CallRecordWriteStub()
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| D | assembler-arm.cc | 3128 void Assembler::vneg(const DwVfpRegister dst, const DwVfpRegister src, in vneg() function in v8::internal::Assembler
3144 void Assembler::vneg(const SwVfpRegister dst, const SwVfpRegister src, in vneg() function in v8::internal::Assembler
4204 void Assembler::vneg(QwNeonRegister dst, QwNeonRegister src) { in vneg() function in v8::internal::Assembler
4211 void Assembler::vneg(NeonSize size, QwNeonRegister dst, QwNeonRegister src) { in vneg() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 507 __ vneg(sz, tmp, tmp); \
1340 __ vneg(i.OutputFloatRegister(), i.InputFloatRegister(0)); in AssembleArchInstruction() local
1404 __ vneg(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); in AssembleArchInstruction() local
1838 __ vneg(i.OutputSimd128Register().low(), i.InputSimd128Register(0).low()); in AssembleArchInstruction() local
1839 __ vneg(i.OutputSimd128Register().high(), in AssembleArchInstruction() local
2193 __ vneg(i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
2342 __ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
2539 __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
2710 __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0)); in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/wasm/baseline/arm/ |
| D | liftoff-assembler-arm.h | 403 assm->vneg(sz, tmp, tmp); in EmitSimdShift()
1562 FP32_UNOP(f32_neg, vneg) in I32_BINOP_I()
1569 FP64_UNOP(f64_neg, vneg) in I32_BINOP_I()
2491 vneg(dst.low_fp(), src.low_fp()); in emit_f64x2_neg()
2492 vneg(dst.high_fp(), src.high_fp()); in emit_f64x2_neg()
2675 vneg(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(src)); in emit_f32x4_neg()
3040 vneg(Neon32, liftoff::GetSimd128Register(dst), in emit_i32x4_neg()
3224 vneg(Neon16, liftoff::GetSimd128Register(dst), in emit_i16x8_neg()
3533 vneg(Neon8, liftoff::GetSimd128Register(dst), in emit_i8x16_neg()
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| /third_party/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5063 void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
5064 void vneg(DataType dt, DRegister rd, DRegister rm) { vneg(al, dt, rd, rm); } in vneg() function
5066 void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
5067 void vneg(DataType dt, QRegister rd, QRegister rm) { vneg(al, dt, rd, rm); } in vneg() function
5069 void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm);
5070 void vneg(DataType dt, SRegister rd, SRegister rm) { vneg(al, dt, rd, rm); } in vneg() function
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| D | disasm-aarch32.h | 2084 void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
2086 void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
2088 void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm);
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| D | disasm-aarch32.cc | 5464 void Disassembler::vneg(Condition cond, in vneg() function in vixl::aarch32::Disassembler
5473 void Disassembler::vneg(Condition cond, in vneg() function in vixl::aarch32::Disassembler
5482 void Disassembler::vneg(Condition cond, in vneg() function in vixl::aarch32::Disassembler
23671 vneg(CurrentCond(), in DecodeT32()
24017 vneg(CurrentCond(), in DecodeT32()
27115 vneg(CurrentCond(), in DecodeT32()
27143 vneg(CurrentCond(), in DecodeT32()
41502 vneg(al, dt, DRegister(rd), DRegister(rm)); in DecodeA32()
41525 vneg(al, dt, QRegister(rd), QRegister(rm)); in DecodeA32()
66253 vneg(condition, F32, SRegister(rd), SRegister(rm)); in DecodeA32()
[all …]
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| D | assembler-aarch32.cc | 21719 void Assembler::vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { in vneg() function in vixl::aarch32::Assembler
21757 Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm); in vneg()
21760 void Assembler::vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { in vneg() function in vixl::aarch32::Assembler
21786 Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm); in vneg()
21789 void Assembler::vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) { in vneg() function in vixl::aarch32::Assembler
21807 Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm); in vneg()
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| D | macro-assembler-aarch32.h | 9858 vneg(cond, dt, rd, rm); in Assembler()
9873 vneg(cond, dt, rd, rm); in Assembler()
9888 vneg(cond, dt, rd, rm); in Assembler()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 924 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
929 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
938 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
2553 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
2554 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
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| D | ARMInstrNEON.td | 6059 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
6060 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
6061 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
6062 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
6063 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
6064 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
6069 "vneg", "f32", "$Vd, $Vm", "",
6073 "vneg", "f32", "$Vd, $Vm", "",
6077 "vneg", "f16", "$Vd, $Vm", "",
6082 "vneg", "f16", "$Vd, $Vm", "",
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| D | ARMInstrMVE.td | 2128 def MVE_VNEGs8 : MVE_VABSNEG_int<"vneg", "s8", 0b00, 0b1>;
2129 def MVE_VNEGs16 : MVE_VABSNEG_int<"vneg", "s16", 0b01, 0b1>;
2130 def MVE_VNEGs32 : MVE_VABSNEG_int<"vneg", "s32", 0b10, 0b1>;
3595 def MVE_VNEGf16 : MVE_VABSNEG_fp<"vneg", "f16", 0b01, 0b1>;
3596 def MVE_VNEGf32 : MVE_VABSNEG_fp<"vneg", "f32", 0b10, 0b1>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 941 Mnemonic = "vneg.f64";
945 Mnemonic = "vneg.f32";
9937 "mullb\006vmullt\004vmvn\004vneg\005vnmla\005vnmls\005vnmul\004vorn\004v"
13493 …{ 2876 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondC…
13494 …{ 2876 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondC…
13495 …{ 2876 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondC…
13496 …{ 2876 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondC…
13497 …{ 2876 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCo…
13498 …{ 2876 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCo…
13499 …{ 2876 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondC…
[all …]
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