Home
last modified time | relevance | path

Searched refs:vreg (Results 1 – 25 of 49) sorted by relevance

12

/third_party/mesa3d/src/imagination/rogue/
Drogue_regalloc.c168 _mesa_hash_table_search(reg_ht, &instr->operands[u].vreg.number); in rogue_ra_alloc()
176 range->class = instr->operands[u].vreg.is_vector in rogue_ra_alloc()
181 &instr->operands[u].vreg.number, in rogue_ra_alloc()
184 max_vreg = MAX2(max_vreg, instr->operands[u].vreg.number); in rogue_ra_alloc()
191 assert(range->class == (instr->operands[u].vreg.is_vector in rogue_ra_alloc()
209 const uint32_t *vreg = entry->key; in rogue_ra_alloc() local
213 ra_set_node_class(g, *vreg, class); in rogue_ra_alloc()
250 instr->operands[0].vreg.number, in rogue_ra_alloc()
251 instr->operands[u].vreg.number); in rogue_ra_alloc()
263 uint32_t vreg = *(uint32_t *)entry->key; in rogue_ra_alloc() local
[all …]
Drogue_instr.c198 instr->operands[index].vreg.number = number; in rogue_instr_set_operand_vreg()
199 instr->operands[index].vreg.is_vector = false; in rogue_instr_set_operand_vreg()
222 instr->operands[index].vreg.number = number; in rogue_instr_set_operand_vreg_vec()
223 instr->operands[index].vreg.is_vector = true; in rogue_instr_set_operand_vreg_vec()
224 instr->operands[index].vreg.component = component; in rogue_instr_set_operand_vreg_vec()
Drogue_dump.c102 fprintf(fp, "%zu", operand->vreg.number); in rogue_dump_operand()
103 if (operand->vreg.is_vector) in rogue_dump_operand()
104 fprintf(fp, ".%c", rogue_vector_string[operand->vreg.component]); in rogue_dump_operand()
Drogue_operand.h134 } vreg; member
/third_party/node/deps/v8/src/compiler/backend/
Dspill-placer.h100 int GetOrCreateIndexForLatestVreg(int vreg);
102 bool IsLatestVreg(int vreg) const { in IsLatestVreg() argument
104 vreg_numbers_[assigned_indices_ - 1] == vreg; in IsLatestVreg()
118 void SetSpillRequired(InstructionBlock* block, int vreg,
121 void SetDefinition(RpoNumber block, int vreg);
137 void CommitSpill(int vreg, InstructionBlock* predecessor,
Dspill-placer.cc69 DCHECK(!IsLatestVreg(range->vreg())); in Add()
82 SetSpillRequired(code->InstructionBlockAt(start_block), range->vreg(), in Add()
100 DCHECK(!IsLatestVreg(range->vreg())); in Add()
103 SetSpillRequired(block, range->vreg(), top_start_block_number); in Add()
110 if (!IsLatestVreg(range->vreg())) { in Add()
115 SetDefinition(top_start_block_number, range->vreg()); in Add()
205 int SpillPlacer::GetOrCreateIndexForLatestVreg(int vreg) { in GetOrCreateIndexForLatestVreg() argument
208 if (!IsLatestVreg(vreg)) { in GetOrCreateIndexForLatestVreg()
228 vreg_numbers_[assigned_indices_] = vreg; in GetOrCreateIndexForLatestVreg()
264 void SpillPlacer::SetSpillRequired(InstructionBlock* block, int vreg, in SetSpillRequired() argument
[all …]
Dregister-allocator-verifier.h98 bool IsAliasOf(int vreg) const { return aliases_.count(vreg) > 0; } in IsAliasOf() argument
99 void AddAlias(int vreg) { aliases_.insert(vreg); } in AddAlias() argument
251 void AddDelayedAssessment(InstructionOperand op, int vreg) { in AddDelayedAssessment() argument
254 map_.insert(std::make_pair(op, vreg)); in AddDelayedAssessment()
256 CHECK_EQ(it->second, vreg); in AddDelayedAssessment()
Dmid-tier-register-allocator.cc267 bool TryDeferSpillOutputUntilEntry(int vreg) { in TryDeferSpillOutputUntilEntry() argument
268 if (spilled_vregs_.count(vreg) != 0) return true; in TryDeferSpillOutputUntilEntry()
270 spilled_vregs_.insert(vreg); in TryDeferSpillOutputUntilEntry()
376 int vreg() const { return vreg_; } in vreg() function in v8::internal::compiler::VirtualRegisterData
600 data->spilled_virtual_registers().Add(vreg()); in EnsureSpillRange()
629 vreg()); in TrySpillOnEntryToDeferred()
1359 VirtualRegisterData& vreg, int instr_index);
1360 void AllocateOutput(UnallocatedOperand* operand, VirtualRegisterData& vreg,
1362 void AllocateInput(UnallocatedOperand* operand, VirtualRegisterData& vreg,
1370 VirtualRegisterData& vreg, int instr_index);
[all …]
Dregister-allocator.cc138 DCHECK_EQ(range->vreg(), operand_index); in ArrayFor()
690 if (pos == other_pos) return TopLevel()->vreg() < other->TopLevel()->vreg(); in ShouldBeAllocatedBefore()
695 return TopLevel()->vreg() < other->TopLevel()->vreg(); in ShouldBeAllocatedBefore()
811 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument
813 vreg_(vreg), in TopLevelLiveRange()
951 TRACE_COND(trace_alloc, "Shorten live range %d to [%d\n", vreg(), in ShortenTo()
962 TRACE_COND(trace_alloc, "Ensure live range %d in interval [%d %d[\n", vreg(), in EnsureInterval()
983 TRACE_COND(trace_alloc, "Add to live range %d interval [%d %d[\n", vreg(), in AddUseInterval()
1009 TRACE_COND(trace_alloc, "Add to live range %d use position %d\n", vreg(), in AddUsePosition()
1054 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() in operator <<()
[all …]
Dregister-allocator-verifier.cc172 int vreg = unallocated->virtual_register(); in BuildConstraint() local
173 constraint->virtual_register_ = vreg; in BuildConstraint()
181 if (sequence()->IsFP(vreg)) { in BuildConstraint()
188 DCHECK(!sequence()->IsFP(vreg)); in BuildConstraint()
205 if (sequence()->IsFP(vreg)) { in BuildConstraint()
214 ElementSizeLog2Of(sequence()->GetRepresentation(vreg)); in BuildConstraint()
608 int vreg = pair.second; in VerifyGapMoves() local
617 vreg); in VerifyGapMoves()
622 vreg); in VerifyGapMoves()
Dinstruction-selector-impl.h242 InstructionOperand DefineSameAsFirstForVreg(int vreg) { in DefineSameAsFirstForVreg() argument
243 return UnallocatedOperand(UnallocatedOperand::SAME_AS_INPUT, vreg); in DefineSameAsFirstForVreg()
246 InstructionOperand DefineAsRegistertForVreg(int vreg) { in DefineAsRegistertForVreg() argument
247 return UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg); in DefineAsRegistertForVreg()
250 InstructionOperand UseRegisterForVreg(int vreg) { in UseRegisterForVreg() argument
252 UnallocatedOperand::USED_AT_START, vreg); in UseRegisterForVreg()
Dinstruction-scheduler.cc187 int32_t vreg = UnallocatedOperand::cast(input)->virtual_register(); in AddInstruction() local
188 auto it = operands_map_.find(vreg); in AddInstruction()
/third_party/mesa3d/src/util/tests/
Dregister_allocate_test.cpp99 int vreg = next_vreg++; in TEST_F() local
100 ra_class_add_reg(reg32low, vreg); in TEST_F()
101 ra_add_transitive_reg_conflict(regs, i, vreg); in TEST_F()
108 int vreg = next_vreg++; in TEST_F() local
109 ra_class_add_reg(reg64low, vreg); in TEST_F()
110 ra_add_transitive_reg_conflict(regs, i, vreg); in TEST_F()
111 ra_add_transitive_reg_conflict(regs, (i + 1) % 8, vreg); in TEST_F()
117 int vreg = next_vreg++; in TEST_F() local
118 ra_class_add_reg(reg96, vreg); in TEST_F()
120 ra_add_transitive_reg_conflict(regs, i + j, vreg); in TEST_F()
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-arm64.cc1483 ? vreg(code).Get<float>(lane) in PrintVRegisterFPHelper()
1484 : vreg(code).Get<double>(lane); in PrintVRegisterFPHelper()
3126 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing1Source()
3127 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing1Source()
3142 fabs_(vform, vreg(fd), vreg(fn)); in VisitFPDataProcessing1Source()
3148 fneg(vform, vreg(fd), vreg(fn)); in VisitFPDataProcessing1Source()
3217 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing2Source()
3218 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing2Source()
3219 SimVRegister& rm = vreg(instr->Rm()); in VisitFPDataProcessing2Source()
3928 SimVRegister& rd = vreg(instr->Rd()); in VisitNEON2RegMisc()
[all …]
Dsimulator-arm64.h1003 T vreg(unsigned code) const { in vreg() function
1013 inline SimVRegister& vreg(unsigned code) { return vregisters_[code]; } in vreg() function
1022 uint8_t breg(unsigned code) const { return vreg<uint8_t>(code); } in breg()
1024 float hreg(unsigned code) const { return vreg<uint16_t>(code); } in hreg()
1026 float sreg(unsigned code) const { return vreg<float>(code); } in sreg()
1028 uint32_t sreg_bits(unsigned code) const { return vreg<uint32_t>(code); } in sreg_bits()
1030 double dreg(unsigned code) const { return vreg<double>(code); } in dreg()
1032 uint64_t dreg_bits(unsigned code) const { return vreg<uint64_t>(code); } in dreg_bits()
1034 qreg_t qreg(unsigned code) const { return vreg<qreg_t>(code); } in qreg()
1039 T vreg(unsigned size, unsigned code) const { in vreg() function
[all …]
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_finalize.cpp516 unsigned vreg = v->gpr.sel(); in copy_fetch_src() local
520 reg = vreg; in copy_fetch_src()
521 else if ((unsigned)reg != vreg) { in copy_fetch_src()
623 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
627 reg = vreg; in finalize_fetch()
628 else if ((unsigned)reg != vreg) { in finalize_fetch()
670 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
674 reg = vreg; in finalize_fetch()
675 else if ((unsigned)reg != vreg) { in finalize_fetch()
747 unsigned vreg = v->gpr.sel(); in finalize_cf() local
[all …]
/third_party/node/deps/v8/src/codegen/x64/
Dassembler-x64-inl.h188 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument
194 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
197 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
201 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument
205 XMMRegister ivreg = XMMRegister::from_code(vreg.code()); in emit_vex_prefix()
210 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, Operand rm, in emit_vex_prefix() argument
216 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
219 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
223 void Assembler::emit_vex_prefix(Register reg, Register vreg, Operand rm, in emit_vex_prefix() argument
227 XMMRegister ivreg = XMMRegister::from_code(vreg.code()); in emit_vex_prefix()
Dassembler-x64.cc3874 void Assembler::bmi1q(byte op, Register reg, Register vreg, Register rm) { in bmi1q() argument
3877 emit_vex_prefix(reg, vreg, rm, kLZ, kNoPrefix, k0F38, kW1); in bmi1q()
3882 void Assembler::bmi1q(byte op, Register reg, Register vreg, Operand rm) { in bmi1q() argument
3885 emit_vex_prefix(reg, vreg, rm, kLZ, kNoPrefix, k0F38, kW1); in bmi1q()
3890 void Assembler::bmi1l(byte op, Register reg, Register vreg, Register rm) { in bmi1l() argument
3893 emit_vex_prefix(reg, vreg, rm, kLZ, kNoPrefix, k0F38, kW0); in bmi1l()
3898 void Assembler::bmi1l(byte op, Register reg, Register vreg, Operand rm) { in bmi1l() argument
3901 emit_vex_prefix(reg, vreg, rm, kLZ, kNoPrefix, k0F38, kW0); in bmi1l()
4026 void Assembler::bmi2q(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2q() argument
4030 emit_vex_prefix(reg, vreg, rm, kLZ, pp, k0F38, kW1); in bmi2q()
[all …]
/third_party/optimized-routines/string/arm/
Dmemcpy.S85 .macro cpy_line_vfp vreg, base
86 vstr \vreg, [dst, #\base]
87 vldr \vreg, [src, #\base]
94 vstr \vreg, [dst, #\base + 32]
95 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
104 .macro cpy_tail_vfp vreg, base
105 vstr \vreg, [dst, #\base]
106 vldr \vreg, [src, #\base]
113 vstr \vreg, [dst, #\base + 32]
/third_party/node/deps/v8/src/compiler/
Dgraph-visualizer.cc435 void PrintLiveRange(const LiveRange* range, const char* type, int vreg);
722 int vreg = range->vreg(); in PrintLiveRangeChain() local
725 PrintLiveRange(child, type, vreg); in PrintLiveRangeChain()
730 int vreg) { in PrintLiveRange() argument
733 os_ << vreg << ":" << range->relative_id() << " " << type; in PrintLiveRange()
766 os_ << " " << parent->vreg() << ":" << parent->relative_id(); in PrintLiveRange()
1017 int vreg = top_level_live_range_json.range_.vreg(); in operator <<() local
1019 os << "\"" << (vreg > 0 ? vreg : -vreg) << "\":{ \"child_ranges\":["; in operator <<()
1138 int vreg = ConstantOperand::cast(op)->virtual_register(); in operator <<() local
1140 os << "\"text\": \"v" << vreg << "\","; in operator <<()
[all …]
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_optimizer.cpp536 old_use(old_use_), vreg(vreg_), index(i),success(false) {} in ReplaceConstSource()
543 RegisterVec4& vreg; member in r600::ReplaceConstSource
623 vreg[index]->del_use(old_use); in visit()
624 auto reg = new Register(vreg.sel(), override_chan, vreg[index]->pin()); in visit()
625 vreg.set_value(index, reg); in visit()
Dsfn_valuefactory.cpp373 auto vreg = new Register( sel, chan, pin_channel); in dest() local
375 vreg->set_is_ssa(true); in dest()
376 m_registers[key] = vreg; in dest()
377 sfn_log << SfnLog::reg << "allocate Ssa " << key << ":" << *vreg << "\n"; in dest()
378 return vreg; in dest()
/third_party/vixl/test/aarch64/
Dtest-utils-aarch64.cc214 const VRegister& vreg) { in Equal128() argument
215 VIXL_ASSERT(vreg.Is128Bits()); in Equal128()
219 QRegisterValue result = core->qreg(vreg.GetCode()); in Equal128()
292 const VRegister& vreg) { in Equal64() argument
293 VIXL_ASSERT(vreg.Is64Bits()); in Equal64()
294 uint64_t result = core->dreg_bits(vreg.GetCode()); in Equal64()
/third_party/node/deps/v8/src/codegen/ia32/
Dassembler-ia32.cc3111 void Assembler::bmi1(byte op, Register reg, Register vreg, Operand rm) { in bmi1() argument
3114 emit_vex_prefix(vreg, kLZ, kNoPrefix, k0F38, kW0); in bmi1()
3146 void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, in bmi2() argument
3150 emit_vex_prefix(vreg, kLZ, pp, k0F38, kW0); in bmi2()
3158 Register vreg = Register::from_code(0); // VEX.vvvv unused in rorx() local
3160 emit_vex_prefix(vreg, kLZ, kF2, k0F3A, kW0); in rorx()
3254 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp, in emit_vex_prefix() argument
3260 EMIT(w | ((~vreg.code() & 0xF) << 3) | l | pp); in emit_vex_prefix()
3263 EMIT(((~vreg.code()) << 3) | l | pp); in emit_vex_prefix()
3267 void Assembler::emit_vex_prefix(Register vreg, VectorLength l, SIMDPrefix pp, in emit_vex_prefix() argument
[all …]
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
Dgpir.h190 } vreg; member

12